公开(公告)号：US20240111533A1

公开(公告)日：2024-04-04

申请号：US18534012

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Dan BAUM ,  Alexander F. HEINECKE ,  Elmoustaha OULD-AHMED-VALL ,  Yuri GEBIL ,  Raanan SADE

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20230069000A1

公开(公告)日：2023-03-02

申请号：US17463398

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Alexander HEINECKE ,  Menachem ADELMAN ,  Robert VALENTINE ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Mark CHARNEY ,  Evangelos GEORGANAS ,  Dhiraj KALAMKAR ,  Christopher HUGHES ,  Cristina ANDERSON

IPC: G06F9/30

Abstract: Techniques for performing arithmetic operations on BF16 values are described. An exemplary instruction includes fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on BF16 data elements in that data element position in BF16 format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand.

公开(公告)号：US20230060146A1

公开(公告)日：2023-03-02

申请号：US17463390

申请日：2021-08-31

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Alexander HEINECKE ,  Robert VALENTINE ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Mark CHARNEY ,  Evangelos GEORGANAS ,  Dhiraj KALAMKAR ,  Christopher HUGHES ,  Cristina ANDERSON

IPC: G06F9/30

Abstract: Techniques for BF16 classification or manipulation using single instructions are described. An exemplary instruction includes fields for an opcode, an identification of a location of a packed data source operand, an indication of one or more classification checks to perform, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operand, a classification according to the indicated one or more classification checks and store a result of the classification in a corresponding data element position of the destination operand.

公开(公告)号：US20220326949A1

公开(公告)日：2022-10-13

申请号：US17845103

申请日：2022-06-21

Applicant: Intel Corporation

Inventor： Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Raanan SADE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to systems and methods for performing 16-bit floating-point vector dot product instructions. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of 16-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.

公开(公告)号：US20220300286A1

公开(公告)日：2022-09-22

申请号：US17833643

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Stanislav SHWARTSMAN

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, performing a matrix operation of zeroing a matrix in response to a single instruction. For example, a processor detailed which includes decode circuitry to decode an instruction having fields for an opcode and a source/destination matrix operand identifier; and execution circuitry to execute the decoded instruction to zero each data element of the identified source/destination matrix.

公开(公告)号：US20220291926A1

公开(公告)日：2022-09-15

申请号：US17706413

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Rinat RAPPOPORT ,  Jesus CORBAL ,  Stanislav SHWARTSMAN ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Dan BAUM ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

公开(公告)号：US20220236989A1

公开(公告)日：2022-07-28

申请号：US17587637

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

公开(公告)号：US20210318874A1

公开(公告)日：2021-10-14

申请号：US17240882

申请日：2021-04-26

Applicant: INTEL CORPORATION

Inventor： Bret TOLL ,  Christopher J. HUGHES ,  Dan BAUM ,  Elmoustapha OULD-AHMED-VALL ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US20210216315A1

公开(公告)日：2021-07-15

申请号：US17152160

申请日：2021-01-19

Applicant: INTEL CORPORATION

Inventor： Bret TOLL ,  Alexander F. HEINECKE ,  Christopher J. HUGHES ,  Ronen ZOHAR ,  Michael ESPIG ,  Dan BAUM ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F12/06 ,  G06F12/02 ,  G06F9/38 ,  G06T1/20

Abstract: Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

公开(公告)号：US20210157589A1

公开(公告)日：2021-05-27

申请号：US17167863

申请日：2021-02-04

Applicant: Intel Corporation

Inventor： Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Raanan SADE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to systems and methods for performing 16-bit floating-point vector dot product instructions. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply N pairs of 16-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.