中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

49 records (took 0.022 seconds)

    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS
    3.
    发明申请
    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS 有权

    公开(公告)号：US20220100515A1

    公开(公告)日：2022-03-31

    申请号：US17549221

    申请日：2021-12-13

    Applicant: Intel Corporation

    Inventor： Bret TOLL ,  Christopher J. HUGHES ,  Dan BAUM ,  Elmoustapha OULD-AHMED-VALL ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

    IPC: G06F9/30

    Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

    SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS
    5.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS 审中-公开

    公开(公告)号：US20190042261A1

    公开(公告)日：2019-02-07

    申请号：US16131382

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Christopher J. HUGHES ,  Bret TOLL ,  Dan BAUM ,  Elmoustapha OULD-AHMED-VALL ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying horizontal tile operations. In one example, a processor includes fetch circuitry to fetch an instruction specifying a horizontal tile operation, a location of a M by N source matrix comprising K groups of elements, and locations of K destinations, wherein each of the K groups of elements comprises the same number of elements, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction by generating K results, each result being generated by performing the specified horizontal tile operation across every element of a corresponding group of the K groups, and writing each generated result to a corresponding location of the K specified destination locations.

    APPARATUSES, METHODS, AND SYSTEMS TO ACCELERATE STORE PROCESSING
    6.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS TO ACCELERATE STORE PROCESSING 审中-公开

    公开(公告)号：US20240211262A1

    公开(公告)日：2024-06-27

    申请号：US18419059

    申请日：2024-01-22

    Applicant: Intel Corporation

    Inventor： Ahmad YASIN ,  Raanan SADE ,  Liron ZUR ,  Igor YANOVER ,  Joseph NUZMAN

    IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/348

    Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

Patent Agency Ranking