公开(公告)号：US10185619B2

公开(公告)日：2019-01-22

申请号：US15087797

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert Swanson ,  Mohan J. Kumar

IPC: G06F11/07 ,  G06F12/0804

Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

公开(公告)号：US10157005B2

公开(公告)日：2018-12-18

申请号：US15282463

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Tony S. Baker ,  Theodros Yigzaw ,  Chris Ackles ,  Celeste M. Brown

IPC: G06F3/06 ,  G11C13/00

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.