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公开(公告)号：US20190272574A1
公开(公告)日：2019-09-05
申请号：US16398983
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Robert Bruce Bahnsen , Robert S. Gittins , Robert Swanson , Mallik Bulusu
Abstract: Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.
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公开(公告)号：US09977682B2
公开(公告)日：2018-05-22
申请号：US14964067
申请日：2015-12-09
Applicant: Intel Corporation
Inventor： Robert Swanson , Vincent J. Zimmer
CPC classification number: G06F9/4406 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/55 , G06F21/575 , G06F21/577 , G06F21/74
Abstract: Various configurations and methods for disabling system management mode (SMM) and verifying a disabled status of SMM in a computing system are disclosed. In various examples, SMM may be disabled through a hardware strap, soft-straps, or firmware functions, and the indication of the SMM disabled status may be included in a model specific register (MSR) value accessible to the central processing unit (CPU). Additionally, techniques for verifying whether SMM is disabled in hardware or firmware, preventing access of SMM functionality, and handling secure software operations are disclosed.
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公开(公告)号：US20170168844A1
公开(公告)日：2017-06-15
申请号：US14964067
申请日：2015-12-09
Applicant: Intel Corporation
Inventor： Robert Swanson , Vincent J. Zimmer
CPC classification number: G06F9/4406 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/55 , G06F21/575 , G06F21/577 , G06F21/74
Abstract: Various configurations and methods for disabling system management mode (SMM) and verifying a disabled status of SMM in a computing system are disclosed. In various examples, SMM may be disabled through a hardware strap, soft-straps, or firmware functions, and the indication of the SMM disabled status may be included in a model specific register (MSR) value accessible to the central processing unit (CPU). Additionally, techniques for verifying whether SMM is disabled in hardware or firmware, preventing access of SMM functionality, and handling secure software operations are disclosed.
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Patent Agency Ranking
公开(公告)号：US11042921B2
公开(公告)日：2021-06-22
申请号：US16398983
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Robert Bruce Bahnsen , Robert S. Gittins , Robert Swanson , Mallik Bulusu
Abstract: Various systems and methods for obtaining vendor information using mobile internet devices are described herein. An inquiry for a product or service is received from a user. A location for the receipt of the product or service is received. Vendor information of a vendor of the product or service proximate to the location is determined, with the vendor information including a price for the product or service, and a wait time to receive the product or service. The vendor information is then transmitted to the user.
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公开(公告)号：US10528398B2
公开(公告)日：2020-01-07
申请号：US15721372
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Robert Swanson , Anil Keshavamurthy , Eswaramoorthi Nallusamy
IPC: G06F9/50 , G06F9/455 , G06F9/4401 , G06F9/54
Abstract: Systems, apparatuses and methods may provide for technology that detects an initiation of a reset flow in a network edge computing system and determines one or more attributes of one or more long flow instructions during the reset flow, wherein the one or more attributes include a latency of the one or more long flow instructions. Additionally, the one or more attributes may be documented via an interface that is accessible by one or more of an operating system or a hypervisor associated with the network edge computing system.
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6.发明授权公开(公告)号：US10185619B2
公开(公告)日：2019-01-22
申请号：US15087797
申请日：2016-03-31
Applicant: INTEL CORPORATION
Inventor： Theodros Yigzaw , Ashok Raj , Robert Swanson , Mohan J. Kumar
IPC: G06F11/07 , G06F12/0804
Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
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7.发明申请公开(公告)号：US20190101965A1
公开(公告)日：2019-04-04
申请号：US15721372
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Robert Swanson , Anil Keshavamurthy , Eswaramoorthi Nallusamy
Abstract: Systems, apparatuses and methods may provide for technology that detects an initiation of a reset flow in a network edge computing system and determines one or more attributes of one or more long flow instructions during the reset flow, wherein the one or more attributes include a latency of the one or more long flow instructions. Additionally, the one or more attributes may be documented via an interface that is accessible by one or more of an operating system or a hypervisor associated with the network edge computing system.
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公开(公告)号：US09891686B2
公开(公告)日：2018-02-13
申请号：US14038347
申请日：2013-09-26
Applicant: INTEL CORPORATION
Inventor： Janusz Jurski , Robert Swanson , Anil Kumar , Mariusz Oriol , Waldemar Piotrewicz
Abstract: An apparatus and system for throttling I/O devices in a computer system is provided. In an example, a method for throttling device power demand during critical power events. The method includes detecting a critical power event and issuing a signal to system devices to defer optional transactions during the critical power event.
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