Semiconductor device including optimized gate stack profile

    公开(公告)号:US09929250B1

    公开(公告)日:2018-03-27

    申请号:US15277722

    申请日:2016-09-27

    CPC classification number: H01L29/66545 H01L29/42376 H01L29/4966

    Abstract: A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor substrate that extends along a first axis to define a length and a second axis opposite the first axis to define a height. A channel region is interposed between opposing source/drain regions, and a gate stack is atop the semiconductor substrate. The gate stack includes an electrically conductive gate atop the channel region. The electrically conductive gate includes sidewalls extending between a base and an upper surface to define a gate height. A gate length of the electrically conductive gate continuously increases as the gate height increases from the base to the upper surface.

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