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    Media capture device with power saving and encryption features for partitioned neural network
    1.
    发明授权
    Media capture device with power saving and encryption features for partitioned neural network 有权

    公开(公告)号：US11948059B2

    公开(公告)日：2024-04-02

    申请号：US16952314

    申请日：2020-11-19

    申请人： International Business Machines Corporation

    发明人： Xin Zhang ,  Xiaodong Cui ,  Jin Ping Han

    IPC分类号： G06N3/04 ,  G06F1/3246 ,  G06F1/3287 ,  G06F21/62

    CPC分类号： G06N3/04 ,  G06F1/3246 ,  G06F1/3287 ,  G06F21/6209

    摘要： A method for power saving and encryption during analysis of media captured by an information capture device using a partitioned neural network includes replicating, by an information capture device, an artificial neural network (ANN) from a computer server to the information capture device. The ANN on the computer server and a replicated ANN, both, include M layers. The method further includes, in response to captured data being input to be processed, partially processing, by the information capture device, the captured data by executing a first k layers using the replicated ANN, wherein only the k layers are selected to execute on the information capture device. The method further includes transmitting, by the information capture device, an output of the k-th layer to the computer server, which partially processes the captured data by executing the remainder of the M layers using the ANN and the output of the k-th layer.

    Multi-terminal cross-point synaptic device using nanocrystal dot structures
    2.
    发明授权
    Multi-terminal cross-point synaptic device using nanocrystal dot structures 有权

    公开(公告)号：US11195089B2

    公开(公告)日：2021-12-07

    申请号：US16021824

    申请日：2018-06-28

    申请人： International Business Machines Corporation

    发明人： Kevin K. Chan ,  Martin M. Frank ,  Jin Ping Han

    IPC分类号： G06N3/06 ,  G06N3/08 ,  G06N3/063

    摘要： Described herein is a crossbar array that includes a cross-point synaptic device at each of a plurality of crosspoints. The cross-point synaptic device includes a weight storage element comprising a set of nanocrystal dots. Further, the cross-point synaptic device includes at least three terminals for interacting with the weight storage element, wherein a weight is stored in the weight storage element by sending a first electric pulse via a gate terminal from the at least three terminals, the first electric pulse causes the nanocrystal dots to store a corresponding charge, and the weight is erased from the weight storage element by sending a second electric pulse via the gate terminal, the second electric pulse having an opposite polarity of the first electric pulse.

    Image sensor with analog sample and hold circuit control for analog neural networks
    3.
    发明授权
    Image sensor with analog sample and hold circuit control for analog neural networks 有权

    公开(公告)号：US10708522B2

    公开(公告)日：2020-07-07

    申请号：US16100249

    申请日：2018-08-10

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Xin Zhang ,  Jin Ping Han ,  Dennis M. Newns ,  Xiaodong Cui

    IPC分类号： H04N5/341 ,  H01L25/16 ,  H04N5/232 ,  H04N5/235

    摘要： According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

    One-transistor synapse cell with weight adjustment
    4.
    发明授权
    One-transistor synapse cell with weight adjustment 有权

    公开(公告)号：US10395713B2

    公开(公告)日：2019-08-27

    申请号：US15859583

    申请日：2017-12-31

    申请人： International Business Machines Corporation

    发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

    IPC分类号： G06N3/06 ,  G11C11/22 ,  H03K19/177

    摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

    CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME
    8.
    发明申请
    CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME 审中-公开

    公开(公告)号：US20190378555A1

    公开(公告)日：2019-12-12

    申请号：US16550809

    申请日：2019-08-26

    申请人： International Business Machines Corporation

    发明人： Jin Ping Han ,  Xiao Sun ,  Teng Yang

    IPC分类号： G11C11/22 ,  H03K19/177

    摘要： Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.