公开(公告)号：US10372416B2

公开(公告)日：2019-08-06

申请号：US15499893

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314934A1

公开(公告)日：2018-11-01

申请号：US15499900

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsh ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314932A1

公开(公告)日：2018-11-01

申请号：US15499898

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Tomer Schwartz ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/08 ,  G06T1/20 ,  G06F7/60

CPC classification number: G06N3/06 ,  G06N3/0454

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to generate synthetic data for a generative adversarial network (GAN) using the plurality of execution units. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180314899A1

公开(公告)日：2018-11-01

申请号：US15499889

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Jeremie Dreyfuss ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Eran Ben-Avi ,  Neta Zmora ,  Tomer Schwartz

IPC: G06K9/00 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180082212A1

公开(公告)日：2018-03-22

申请号：US15270057

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Amitai Armon

IPC: G06N99/00 ,  G06F15/82

CPC classification number: G06N20/00 ,  G06F15/82

Abstract: An optimization of running time for performing a machine learning algorithm on a processor architecture may be performed and include determining a plurality of parameters to be configured in the machine learning algorithm, and initiating, in the optimization, a plurality of iterations of performance of the machine learning algorithm by the processor architecture. Each of the iterations may include detecting a running time of an immediately preceding one of the iterations, changing a value of one of the parameters used in the immediately preceding iteration to form a new set of values, where the value is changed based on the detected running time of the immediately preceding iteration and according to a downhill simplex algorithm. An optimal set of values for the parameters may be determined based on the plurality of iterations to realize a minimum running time to complete performance of the machine learning algorithm by the processor architecture.

公开(公告)号：US12033063B2

公开(公告)日：2024-07-09

申请号：US18174275

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/06 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240160910A1

公开(公告)日：2024-05-16

申请号：US18527734

申请日：2023-12-04

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

CPC classification number: G06N3/063 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230281435A1

公开(公告)日：2023-09-07

申请号：US18174275

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US11704564B2

公开(公告)日：2023-07-18

申请号：US17404153

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/00 ,  G06N20/10

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11620766B2

公开(公告)日：2023-04-04

申请号：US17344639

申请日：2021-06-10

Applicant: INTEL CORPORATION

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/084 ,  G06N3/088

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer.