公开(公告)号：US08037085B2

公开(公告)日：2011-10-11

申请号：US12129976

申请日：2008-05-30

申请人： Jason R. Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Fadi Z. Zaraket

发明人： Jason R. Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Fadi Z. Zaraket

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/504

摘要： A method for performing verification includes selecting a first set containing a seed register and adding to a second set a result of a subtraction of a fanout of the first set from a fanin of the first set. A third set is rendered equal to a result of a subtraction of a fanin of the second set from a fanout of the second set, and whether a combination of the first set and the third set is equivalent to the first set is determined. In response to determining that the combination of the first set and the second set is not equivalent to the first set, a min-cut of the first set and the second set containing a minimal set of predicates between a first component and the logic to which the component fans out, wherein the logic is bordered by the second set is returned.

摘要翻译： 一种用于执行验证的方法包括：选择包含种子寄存器的第一集合，并且从第一组的扇区中减去第一组的扇出结果，向第二组添加结果。 第三组被赋予等于从第二组的扇出中减去第二组的扇形的结果，以及第一组和第三组的组合是否等同于第一组的结果。 响应于确定第一集合和第二集合的组合不等同于第一集合，第一集合和第二集合的最小化包含第一组件和逻辑之间的最小一组谓词 组件风扇出来，其中返回逻辑与第二组相邻的逻辑。

公开(公告)号：US20080235637A1

公开(公告)日：2008-09-25

申请号：US12047189

申请日：2008-06-09

申请人： JASON R. BAUMGARTNER ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

发明人： JASON R. BAUMGARTNER ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements are received. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results.

摘要翻译： 一种用于保存关键输入的方法，系统和计算机程序产品。 根据本发明的实施例，接收包括不能被消除的一个或多个主要输入，可以被消除的一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。 识别包括一个或多个切割门的所述初始设计的切割，以及根据所述一个或多个主要输入而不能被消除的一个或多个可生产到所述一个或多个切割门的值的关系，所述一个或多个主要 可以消除的输入和所述一个或多个状态元素被计算。 所述关系被合成以形成栅极集合，并且从所述栅极集合形成抽象设计。 对所述抽象设计进行验证以产生验证结果。

公开(公告)号：US07788615B2

公开(公告)日：2010-08-31

申请号：US11938612

申请日：2007-11-12

申请人： Jason Raymond Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Jiazhao Xu

发明人： Jason Raymond Baumgartner ,  Hari Mony ,  Viresh Paruthi ,  Jiazhao Xu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/504

摘要： A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

摘要翻译： 公开了一种用于验证设计符合期望属性的方法，系统和计算机程序产品。 该方法包括接收设计，设计的第一初始状态和关于设计的验证的属性。 设计的第一初始状态被扩展以创建包含从设计的第一初始状态可访问的一个或多个状态的第一初始状态的超集。 合成超集以定义设计的第二初始状态。 超设计对设计的应用通过将切入点插入到超集中来获得修改后的超集，并且参考修改后的超集来验证该属性。

公开(公告)号：US20080109769A1

公开(公告)日：2008-05-08

申请号：US12013220

申请日：2008-01-11

申请人： Jason Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, system and computer program product for reversing effects of reparameterization is disclosed. The method comprises receiving an original design, an abstracted design, and a first trace over the abstracted design. One or more conditional values are populated into the first trace over the abstracted design, and a k-step satisfiability check is cast to obtain a second trace. One or more calculated values are concatenated to an initial gate set in the second trace with one or more established values to a generated subset of the initial design in the abstracted trace to form a new trace, and one or more effects of a reparameterization are reversed by returning the new trace over the initial design.

公开(公告)号：US20080104560A1

公开(公告)日：2008-05-01

申请号：US11971283

申请日：2008-01-09

申请人： Jason Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A method, system and computer program product for performing parametric reduction of sequential designs is disclosed. The method comprises receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.

摘要翻译： 公开了一种用于执行顺序设计的参数化减少的方法，系统和计算机程序产品。 该方法包括接收包括一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。 识别包括一个或多个切割门的初始设计的切割，并且计算在一个或多个主要输入和一个或多个状态元素方面可生产到一个或多个切割门的一个或多个值的关系。 该关系被合成以形成一个栅极集合，并且从栅极集合形成抽象的设计。 对抽象设计进行验证以生成验证结果。

公开(公告)号：US20080104559A1

公开(公告)日：2008-05-01

申请号：US11969761

申请日：2008-01-04

申请人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more targets from the first target set and the structural product extraction is recursed for one or more next-state functions of a subset of the one or more registers. A sum-of-products form is recursed from the structural product extraction for one or more next-state functions of a subset of the one or more registers and a product-of-sums form of a result of the second recursing is decomposed to generate a decomposition of the product-of-sums form. The decomposition of the product-of-sums form is synthesized into a second target set and a subset of the second target set to recursively decompose is chosen. In response to the subset of the second target set being nonempty, the first target set is recursively decomposed and, in response to the second target set being empty, verification is applied to the second target set.

摘要翻译： 公开了一种用于执行电子设计验证的方法，系统和计算机程序产品。 该方法包括接收设计，其中该设计包括第一目标组和包括一个或多个寄存器的第一寄存器组。 从第一目标集合的一个或多个目标形成结构性产品提取，并且针对一个或多个寄存器的子集的一个或多个下一个状态函数递归结构乘积提取。 从一个或多个寄存器的子集的一个或多个下一个状态函数的结构性产品提取中递归产生积和形式，并且将第二次递归的结果的乘积形式分解生成 产品总和形式的分解。 求和形式的分解被合成为第二目标集合，并且选择第二目标集合的递归分解的子集。 响应于第二目标集合的子集是非空的，第一目标集被递归地分解，并且响应于第二目标集合为空，将验证应用于第二目标集合。

公开(公告)号：US20080104558A1

公开(公告)日：2008-05-01

申请号：US11969741

申请日：2008-01-04

申请人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, wherein the design includes a first target set and a first register set including one or more registers. A structural product extraction is formed from one or more targets from the first target set and the structural product extraction is recursed for one or more next-state functions of a subset of the one or more registers. A sum-of-products form is recursed from the structural product extraction for one or more next-state functions of a subset of the one or more registers and a product-of-sums form of a result of the second recursing is decomposed to generate a decomposition of the product-of-sums form. The decomposition of the product-of-sums form is synthesized into a second target set and a subset of the second target set to recursively decompose is chosen. In response to the subset of the second target set being nonempty, the first target set is recursively decomposed and, in response to the second target set being empty, verification is applied to the second target set.

公开(公告)号：US07367002B2

公开(公告)日：2008-04-29

申请号：US11105615

申请日：2005-04-14

申请人： Jason Raymond Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Raymond Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045 ,  G06F17/504

摘要： A method, system and computer program product for performing parametric reduction of sequential designs. According to an embodiment of the present invention, the method includes receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.

摘要翻译： 一种用于执行顺序设计的参数化减少的方法，系统和计算机程序产品。 根据本发明的实施例，该方法包括接收包括一个或多个主要输入，一个或多个目标以及一个或多个状态元素的初始设计。 识别包括一个或多个切割门的初始设计的切割，并且计算在一个或多个主要输入和一个或多个状态元素方面可生产到一个或多个切割门的一个或多个值的关系。 该关系被合成以形成一个栅极集合，并且从栅极集合形成抽象的设计。 对抽象设计进行验证以生成验证结果。

公开(公告)号：US07350179B2

公开(公告)日：2008-03-25

申请号：US11105618

申请日：2005-04-14

申请人： Jason Raymond Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Raymond Baumgartner ,  Geert Janssen ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.

摘要翻译： 公开了一种用于执行表示的综合的方法，系统和计算机程序产品。 该方法包括接收关系的表示，并且构建表示一个或多个所选父路径的OR函数的门到所述关系的所述表示的节点中。 执行表示所述OR函数的所述门的合成门，并且通过在所述关系的所述表示中迭代所述构建步骤和所述创建步骤对一个或多个变量进行迭代来合成关系表示集合，以累加合成门集合，其合成 返回门组。

公开(公告)号：US20080072186A1

公开(公告)日：2008-03-20

申请号：US11944668

申请日：2007-11-26

申请人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

发明人： Jason Baumgartner ,  Robert Kanzelman ,  Hari Mony ,  Viresh Paruthi

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.

摘要翻译： 公开了一种用于减少包含AND和OR门的结构设计表示中的子表达式的方法，系统和计算机程序产品。 该方法包括接收初始设计，其中初始设计表示包含与门的电子电路。 选择用于从一组适用的简化模式进行初始设计的第一简化模式，其中所述简化模式是AND / OR简化模式，并且执行根据第一简化模式的初始设计的简化以生成缩减设计 。 确定减小设计的尺寸是否小于初始设计的尺寸，并且响应于确定减小的设计的尺寸小于初始设计的尺寸，初始设计被替换为简化的设计 。