公开(公告)号：US07065654B1

公开(公告)日：2006-06-20

申请号：US09852372

申请日：2001-05-10

申请人： Dale E. Gulick ,  Geoffrey S. Strongin

发明人： Dale E. Gulick ,  Geoffrey S. Strongin

IPC分类号： H04L9/00

CPC分类号： G06F21/85 ,  G06F21/72

摘要： A system and method for secure computing. The system includes a processor, one or more secured assets coupled to the processor, and security hardware. The processor is configured to operate in various operating modes, including a secure operating mode. The security hardware is configured to control access to the secured assets dependant upon the operating mode of the processor. The security hardware is configured to allow access to the secure assets in the secure operating mode, preferably only in the secure operating mode. The method includes switching the computer system between operating modes, while allowing or restricting access to the secured assets based on the operating modes. The second operating mode comprises a secure operating mode. The method restricts access to the secured assets in the first operating mode and permits access to the secured assets in the secure operating mode.

摘要翻译： 一种用于安全计算的系统和方法。 该系统包括处理器，耦合到处理器的一个或多个安全资产以及安全硬件。 处理器被配置为在各种操作模式下操作，包括安全操作模式。 安全硬件被配置为根据处理器的操作模式控制对安全资产的访问。 安全硬件被配置为允许以安全操作模式访问安全资产，优选仅在安全操作模式下。 该方法包括在操作模式之间切换计算机系统，同时基于操作模式允许或限制对安全资产的访问。 第二操作模式包括安全操作模式。 该方法限制了在第一操作模式下对安全资产的访问，并允许以安全操作模式访问安全资产。

公开(公告)号：US06968460B1

公开(公告)日：2005-11-22

申请号：US09854040

申请日：2001-05-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F7/58 ,  G06F21/00

CPC分类号： G06F21/6227 ,  G06F7/58 ,  G06F21/78

摘要： A random number generator and method thereto using an entropy register. The method includes providing a first plurality of bit entries in an entropy register and transmitting a bit value from each of a plurality of registers to one of the first plurality of bit entries in the entropy register. The random number generator comprises an entropy register configured to receive bits over a plurality of data lines that each couple to an individual entry in the entropy register. The random number generator may further include an entropy control unit configured to provide a value from the entropy register in response to a request for a random number.

摘要翻译： 一种随机数发生器及其使用熵寄存器的方法。 该方法包括在熵寄存器中提供第一多个比特条目，并将多个寄存器中的每一个的比特值发送到熵寄存器中的第一多个比特条目之一。 随机数生成器包括熵寄存器，其被配置为在多个数据线上接收位，每个数据线耦合到熵寄存器中的单个条目。 随机数生成器还可以包括熵控制单元，其被配置为响应于对随机数的请求从熵寄存器提供值。

公开(公告)号：US06798418B1

公开(公告)日：2004-09-28

申请号：US09577527

申请日：2000-05-24

申请人： Gabriele Sartori ,  Dale E. Gulick

发明人： Gabriele Sartori ,  Dale E. Gulick

IPC分类号： G06F1314

CPC分类号： G09G5/395 ,  G06F3/1431 ,  G09G3/3611 ,  G09G5/06 ,  G09G5/366 ,  G09G2340/02 ,  G09G2340/125

摘要： A graphics subsystem including a RAMDAC for connection to a graphics bus implemented on an integrated circuit chip separate from a graphics processor. In one embodiment, the graphics processor is configured to render digital image information in response to graphics commands and to store the digital image information in a memory. The RAMDAC IC includes a conversion unit, which includes a color mapping unit and a digital-to-analog converter and is configured to convert a representation of the digital image information into one or more analog signals for driving a video display. The graphics subsystem further includes a Direct Memory Access (DMA) controller implemented on the second integrated circuit chip. The DMA controller is configured to generate read requests to retrieve the digital image information stored in the memory to thereby cause the digital image information to be provided to the conversion unit. The DMA controller is further configured to generate write cycles to cause digital RGB display data received from the color mapping unit, in the conversion unit, to be provided for storage in a specified region of memory. In another embodiment, the graphics subsystem may include a digital video interface implemented on the second integrated circuit chip. The digital video interface is configured to receive digital RGB display data from the color mapping unit and to provide an encoded digital video output to a digital video output port. The digital video interface is further configured to receive encoded digital video from a digital video input port and to provide decoded digital display data for storage on devices such as a digital VCR.

摘要翻译： 包括用于连接到与图形处理器分离的集成电路芯片上实现的图形总线的RAMDAC的图形子系统。 在一个实施例中，图形处理器被配置为响应于图形命令呈现数字图像信息并将数字图像信息存储在存储器中。 RAMDAC IC包括转换单元，其包括颜色映射单元和数模转换器，并且被配置为将数字图像信息的表示转换为用于驱动视频显示的一个或多个模拟信号。 图形子系统还包括在第二集成电路芯片上实现的直接存储器访问（DMA）控制器。 DMA控制器被配置为产生读取请求以检索存储在存储器中的数字图像信息，从而使数字图像信息被提供给转换单元。 DMA控制器还被配置为产生写周期以使得从转换单元中的颜色映射单元接收的数字RGB显示数据被提供用于存储在指定的存储器区域中。 在另一个实施例中，图形子系统可以包括在第二集成电路芯片上实现的数字视频接口。 数字视频接口被配置为从彩色映射单元接收数字RGB显示数据，并向数字视频输出端口提供经编码的数字视频输出。 数字视频接口还被配置为从数字视频输入端口接收经编码的数字视频，并提供用于存储在诸如数字VCR的设备上的解码的数字显示数据。

公开(公告)号：US06651128B1

公开(公告)日：2003-11-18

申请号：US09501889

申请日：2000-02-10

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： G06F13/362

摘要： Several different systems and methods are described involving arbitration between asynchronous and isochronous data for access to a data transport resource (e.g., a bus or a memory controller). A first embodiment of a system (e.g., a computer system or a communication system) includes an arbiter coupled to the data transport resource, an asynchronous queue for storing asynchronous data, and an isochronous queue for storing isochronous data. The isochronous queue has a data level range divided into multiple portions. A number of memory locations within the isochronous queue may define the data level range of the isochronous queue. The arbiter arbitrates between the asynchronous queue and the isochronous queue for access to the data transport resource dependent upon the portion of the data level range in which a level of data resides within the isochronous queue. The level of data within the isochronous queue may be a number of memory locations between a write pointer and a read pointer. The arbiter may include a set of arbitration rules, wherein each arbitration rule states conditions used to determine whether data is provided from the isochronous queue or the asynchronous queue. The arbiter may arbitrate between the asynchronous queue and the isochronous queue for access to the data transport resource by: (i) selecting an arbitration rule from the set of arbitration rules dependent upon the portion of the data level range in which the level of data resides within the isochronous queue, and (ii) applying the rule.

摘要翻译： 描述了涉及用于访问数据传输资源（例如，总线或存储器控制器）的异步和同步数据之间的仲裁的若干不同的系统和方法。 系统（例如，计算机系统或通信系统）的第一实施例包括耦合到数据传输资源的仲裁器，用于存储异步数据的异步队列和用于存储等时数据的等时队列。 同步队列具有分为多个部分的数据级别范围。 同步队列内的多个存储器位置可以定义等时队列的数据级别范围。 仲裁器在异步队列和同步队列之间进行仲裁，用于访问数据传输资源，这取决于数据级别的数据级别驻留在同步队列中的部分。 同步队列内的数据级别可以是写指针和读指针之间的多个存储器位置。 仲裁器可以包括一组仲裁规则，其中每个仲裁规则说明用于确定数据是否从等时队列或异步队列提供的条件。 仲裁器可以通过以下方式在异步队列和等时队列之间进行仲裁以访问数据传输资源：（i）根据数据级别所在的数据级别范围的部分从仲裁规则集中选择仲裁规则 在同步队列内，以及（ii）应用规则。

公开(公告)号：US06625743B1

公开(公告)日：2003-09-23

申请号：US09933290

申请日：2001-08-20

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F112

CPC分类号： G06F1/12 ,  G06F13/4217

摘要： A method of synchronizing the generation and consumption of isochronous data in a computer system. In one embodiment, a computer system implements a method comprising providing a plurality of clocks to a plurality of isochronous sinks or sources configured to generate or consume the isochronous data, outputting a master clock signal to the plurality of isochronous sinks or sources, synchronizing said clocks to said master clock signal so that the generation or consumption of the isochronous data is synchronized to said master clock signal, outputting said master clock signal to an interrupt controller, and generating an interrupt based on said master clock signal, wherein a processor schedules one or more tasks that generate or consume data based on said interrupt. The isochronous sinks or sources may also be synched to a multiple of the master clock signal.

摘要翻译： 一种在计算机系统中同步同步数据的生成和消耗的方法。 在一个实施例中，计算机系统实现一种方法，包括向被配置为产生或消耗同步数据的多个同步宿或源提供多个时钟，将主时钟信号输出到多个同步宿或源，同步所述时钟 到所述主时钟信号，使得同步数据的产生或消耗与所述主时钟信号同步，将所述主时钟信号输出到中断控制器，并且基于所述主时钟信号产生中断，其中处理器调度一个或 基于所述中断产生或消耗数据的更多任务。 同步吸收器或源也可以被同步到主时钟信号的倍数。

公开(公告)号：US06457084B1

公开(公告)日：2002-09-24

申请号：US09330528

申请日：1999-06-11

申请人： Dale E. Gulick ,  Geoffrey S. S. Strongin

发明人： Dale E. Gulick ,  Geoffrey S. S. Strongin

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： A computer system includes a first integrated circuit having a first function and a second integrated circuit having a plurality of second functions. A communication link connects the first integrated circuit and the second integrated circuit. The communication link includes at least one logical pipe having a source side on the first circuit and a target side on the second integrated circuit, the one pipe carrying transactions over the communication link between the first function and the second functions. The pipe is identified by a pipe identification carried in the transactions. A target side distributor circuit is coupled between the second functions and the communication link. The target side distributor circuit receives those transactions from the communication link having the pipe identification. The target side distributor circuit provides transactions received from the communication link having the pipe identification to respective ones of the second functions according to an address field included in the transactions.

摘要翻译： 计算机系统包括具有第一功能的第一集成电路和具有多个第二功能的第二集成电路。 通信链路连接第一集成电路和第二集成电路。 通信链路包括至少一个在第一电路上具有源侧和第二集成电路上的目标侧的逻辑管，所述一个管道通过第一功能和第二功能之间的通信链路进行交易。 管道由交易中携带的管道标识识别。 目标侧分配器电路耦合在第二功能和通信链路之间。 目标侧分配器电路从具有管道识别的通信链路接收那些事务。 目标侧分配器电路根据包括在事务中的地址字段，将具有管道标识的通信链路接收的交易提供给相应的第二功能。

公开(公告)号：US06457081B1

公开(公告)日：2002-09-24

申请号：US09330636

申请日：1999-06-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1314

CPC分类号： G06F13/4265

摘要： A read request is sent from a source to a target over a requesting all available data. The requester does not know the amount of data available. The response to the read request includes the available requested data along with an indication of how much available requested data is being returned.

摘要翻译： 读请求通过请求所有可用数据从源发送到目标。 请求者不知道可用数据量。 对读取请求的响应包括可用的请求数据以及返回多少可用请求数据的指示。

公开(公告)号：US06202164B1

公开(公告)日：2001-03-13

申请号：US09109822

申请日：1998-07-02

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： H04L12/40058 ,  G06F1/08 ,  G06F5/06 ,  G06F13/423 ,  G06F2205/061 ,  H04L12/40123 ,  H04N5/232

摘要： A master isochronous clock structure wherein a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.

摘要翻译： 一种主同步时钟结构，其中多个数据总线的帧速率时钟与主时钟信号同步。 主时钟信号可以从计算机系统内的现有时钟信号或从外部源接收的数据中导出。 主时钟信号也可由操作系统调度器用于调度生成或消耗同步数据块的任务。 在替代实施例中，测量器件时钟信号相对于主时钟信号的漂移并用于同步器件时钟信号。 例如，机制可以监视数据缓冲器中的数据级别。 数据缓冲器中的数据电平是产生数据的时钟与消耗数据的时钟之间的漂移的量度。 基于缓冲器中的数据级别，提供同步信息以同步产生和消耗数据的时钟信号的速率。 在一个实施例中，使用数据缓冲器中的数据级别来同步摄像机的时钟。 在另一个实施例中，数据缓冲器中的数据级别用于同步电话编解码器的时钟。

公开(公告)号：US06195749B1

公开(公告)日：2001-02-27

申请号：US09501888

申请日：2000-02-10

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F9445

CPC分类号： G06F9/4401

摘要： A computer system including a memory access controller for using non-system memory storage resources during system boot time. A computer system includes a microprocessor, a system memory and a plurality of peripheral devices coupled to the microprocessor through one or more buses. A system controller and a peripheral bus controller control the buses. Many peripheral device controllers contain buffer memory used during normal system operation, by the peripheral device controllers, to buffer data between the computer system and the peripheral devices. The computer system also includes a memory access controller and a configuration storage unit. The configuration storage unit stores configuration control information which causes control logic to configure the buffer memory. The memory access controller controls accesses to the buffer memory associated with the peripheral devices during system initialization to allow use of the buffer memory as a stack or scratchpad RAM.

摘要翻译： 一种包括用于在系统启动时使用非系统存储器存储资源的存储器访问控制器的计算机系统。 计算机系统包括微处理器，系统存储器和通过一个或多个总线耦合到微处理器的多个外围设备。 系统控制器和外围总线控制器控制总线。 许多外围设备控制器包含在正常系统操作期间由外围设备控制器在计算机系统和外围设备之间缓冲数据所使用的缓冲存储器。 计算机系统还包括存储器访问控制器和配置存储单元。 配置存储单元存储使控制逻辑配置缓冲存储器的配置控制信息。 存储器访问控制器在系统初始化期间控制与外围设备相关联的缓冲存储器的访问，以允许将缓冲存储器用作堆栈或暂存器RAM。

公开(公告)号：US6101560A

公开(公告)日：2000-08-08

申请号：US866652

申请日：1997-05-30

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/385 ,  G06F13/405 ,  Y02B60/1228 ,  Y02B60/1235

摘要： An apparatus includes a game port interface and a bus. The game port interface includes first and second game port portions. The first game port portion is on a first integrated circuit and interfaces to an I/O bus. The second game port portion is on a second integrated circuit and provides I/O terminals to couple the game port interface to a peripheral device. The bus couples the first and second integrated circuits. The bus is for serially transferring game port information between the first and second game port portions.

摘要翻译： 一种装置包括游戏端口接口和总线。 游戏端口接口包括第一和第二游戏端口部分。 第一游戏端口部分在第一集成电路上并且与I / O总线接口。 第二游戏端口部分在第二集成电路上并且提供I / O终端以将游戏端口接口耦合到外围设备。 总线耦合第一和第二集成电路。 总线用于在第一和第二游戏端口部分之间串行传送游戏端口信息。