公开(公告)号：US20210343571A1

公开(公告)日：2021-11-04

申请号：US17377042

申请日：2021-07-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing additional processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one of the first memory cells is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with the processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

公开(公告)号：US11164770B1

公开(公告)日：2021-11-02

申请号：US17372776

申请日：2021-07-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a first single crystal layer; forming first alignment marks and control circuits comprising first single crystal transistors, wherein said control circuits comprise at least two metal layers; forming at least one second level above said control circuits; performing a first etch step within said second level; forming at least one third level above said at least one second level; performing a second etch step within said third level; and performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein said first etch step comprises performing a lithography step aligned to said first alignment marks.

公开(公告)号：US11163112B2

公开(公告)日：2021-11-02

申请号：US17330186

申请日：2021-05-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L27/146 ,  H01L27/15

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11158674B2

公开(公告)日：2021-10-26

申请号：US17121731

申请日：2020-12-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/762 ,  H01L27/24 ,  H01L21/683 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H01L27/22 ,  H01L21/268 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11573 ,  H01L45/00

Abstract: A method for producing a 3D memory device, the method comprising: providing a first level comprising a single crystal layer; forming at least one second level above said first level; performing a first etch step comprising etching holes within said second level; forming at least one third level above said at least one second level; performing a second etch step comprising etching holes within said third level; performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein each of said first memory cells comprise one first transistor, wherein each of said second memory cells comprise one second transistor, wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type, and wherein said forming at least one third level comprises forming a window within said third level to allow lithography alignment through said third level to an alignment mark underneath.

公开(公告)号：US11133344B2

公开(公告)日：2021-09-28

申请号：US17317894

申请日：2021-05-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L23/544 ,  H01L23/00

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of first image sensors and alignment marks; and a third level overlaying the second level, where the third level includes a plurality of second image sensors, where the third level is aligned to the alignment marks, where the second level is bonded to the first level, and where the bonded includes an oxide to oxide bond.

公开(公告)号：US20210294031A1

公开(公告)日：2021-09-23

申请号：US17330186

申请日：2021-05-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon, where the second level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11121121B2

公开(公告)日：2021-09-14

申请号：US16558304

申请日：2019-09-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits includes a first logic circuit and a second logic circuit, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of on-chip RF circuits, and where a portion of interconnections between the first logic circuit and the second logic circuit includes the plurality of on-chip RF circuits.

公开(公告)号：US11107808B1

公开(公告)日：2021-08-31

申请号：US17246612

申请日：2021-05-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L27/02 ,  H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/367

Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer and first transistors, and where the first level includes a second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the second level includes at least one memory array, where the third layer includes crystalline silicon; and where the second level includes at least one SerDes circuit.

公开(公告)号：US11107803B2

公开(公告)日：2021-08-31

申请号：US17214883

申请日：2021-03-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L21/30 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78

Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a memory control on top; and then thinning the memory control, transferring a first memory wafer on top; and then thinning the first memory wafer; and then transferring a second memory wafer on top; and then thinning the second memory wafer. A 3D device, the device including: a first stratum including first bit-cell memory arrays; a second stratum including second bit-cell memory arrays; and a third stratum, where the second stratum overlays the first stratum, where the first stratum overlays the third stratum, where the third stratum includes a plurality of word-line decoders to control the first bit-cell memory arrays and the second bit-cell memory arrays.

公开(公告)号：US20210193498A1

公开(公告)日：2021-06-24

申请号：US17195628

申请日：2021-03-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, and where at least one of the first transistors controls power delivery to at least one of the second transistors.