公开(公告)号：US20060085730A1

公开(公告)日：2006-04-20

申请号：US10954648

申请日：2004-09-30

Applicant: Mark Anders ,  Sanu Mathew ,  Ram Krishnamurthy

Inventor： Mark Anders ,  Sanu Mathew ,  Ram Krishnamurthy

IPC: H03M13/03

CPC classification number: H03M13/6505 ,  H03M13/41 ,  H03M13/4169

Abstract: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.

Abstract translation: 移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

公开(公告)号：US20060069901A1

公开(公告)日：2006-03-30

申请号：US10956164

申请日：2004-09-30

Applicant: Sanu Mathew ,  Mark Anders ,  Sarvesh Kulkarni ,  Ram Krishnamurthy

Inventor： Sanu Mathew ,  Mark Anders ,  Sarvesh Kulkarni ,  Ram Krishnamurthy

IPC: G06F12/04

CPC classification number: G06F7/507 ,  G06F7/508

Abstract: A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic 0 carry-in and a logic 1 carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

Abstract translation: 一种用于地址产生电路的方法和装置。 在一个实施例中，该方法包括计算由多个逻辑地址分量形成的传播信号和生成信号的预定位数的至少一组的进位。 一旦计算了进位，则为逻辑0进位和逻辑1进位产生多个条件和。 随后，从多个条件和中选出一个和，以在第二阶段中从第一阶段的逻辑地址分量和有效地址的第二部分形成有效地址的第一部分。 在一个实施例中，根据一个实施例，使用产生四分之一载波的完全动态的高性能稀疏树加法器电路来形成地址生成电路。 描述和要求保护其他实施例。

公开(公告)号：US06573756B2

公开(公告)日：2003-06-03

申请号：US09919785

申请日：2001-07-31

Applicant: Sanu K. Mathew ,  Mark Anders ,  Ram Krishnamurthy

Inventor： Sanu K. Mathew ,  Mark Anders ,  Ram Krishnamurthy

IPC: H03K1716

CPC classification number: H03K19/0963 ,  H03K19/00361

Abstract: A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

Abstract translation: 在包括高扇形多米诺式门的动态电路中提供噪声消除电路。 噪声消除电路将注入到控制多米诺骨牌的导线的动态电路中的相邻导线的噪声去耦。