公开(公告)号：US5592557A

公开(公告)日：1997-01-07

申请号：US343414

申请日：1995-02-16

Applicant: Djahanyar Chahabadi ,  Matthias Herrmann ,  Lothar Vogt ,  Juergen Kaesser

Inventor： Djahanyar Chahabadi ,  Matthias Herrmann ,  Lothar Vogt ,  Juergen Kaesser

IPC: H03H17/04 ,  H03H17/02 ,  H04B1/10 ,  H04B1/16 ,  H04B1/26 ,  H04B1/64 ,  H04H20/88 ,  H04H5/00

CPC classification number: H04B1/1661 ,  H04B1/1027

Abstract: In a radio receiver with digital signal processing, a stereo multiplex signal received and the useful signals derived therefrom are processed in digital form at a first sampling rate. The subsidiary signals derived from the stereo multiplex signal are at least partly processed at a second sampling rate that is smaller than the first sampling rate. The sampling rate of the processed subsidiary signals are reduced to the first sampling rate with the processed subsidiary signals, acting as control signals with the first sampling rate, affecting the stereo multiplex signal and the useful signals.

Abstract translation: PCT No.PCT / DE94 / 00326 Sec。 371日期1995年2月16日 102（e）日期1995年2月16日PCT 1994年3月22日PCT公布。 出版物WO94 / 22232 日期1994年9月29日在具有数字信号处理的无线电接收机中，接收的立体声多路复用信号和从其导出的有用信号以数字形式以第一采样率进行处理。 从立体声多路复用信号导出的辅助信号至少部分地以小于第一采样率的第二采样率进行处理。 处理的辅助信号的采样率被降低到第一采样率，其中处理的辅助信号用作具有第一采样率的控制信号，影响立体声多路复用信号和有用信号。

公开(公告)号：US5280352A

公开(公告)日：1994-01-18

申请号：US817186

申请日：1992-01-06

Applicant: Matthias Herrmann

Inventor： Matthias Herrmann

IPC: H04N5/04 ,  H04N5/956 ,  H04N7/01

CPC classification number: H04N5/956

Abstract: A digital circuit arrangement for transforming an input digital picture signal onto a reference horizontal synchronizing signal raster derived from the system clock, which input digital picture signal is present at a system clock rate not locked with the input digital picture signal, which includes a correction memory (1), an interpolator/decimator (2), and a control member for the purpose of a transformation which is as insensitive to interference as possible. The control member receives a control deviation signal (d) obtained with the aid of a discriminator (4) by comparing a horizontal synchronizing signal in the input digital picture signal with the reference horizontal synchronizing signal, and the control member applies a first correcting variable (i) to the correction memory (1), the first correcting variable (i) indicating transformation of the input digital picture signal by integral multiples of the system clock period to be performed by the correction memory (1), and the control member also applies a second correcting variable (.alpha..sub.s) to the interpolator/decimator (2), the second correcting variable (.alpha..sub.s) indicating the transformation by fractions of the system clock period to be performed by the interpolator/decimator (2).

Abstract translation: 对于数字电路装置，用于将具有未与其耦合的系统定时存在的数字图像信号变换为从系统定时导出的参考水平同步信号模式，其中具有校正存储器（1）和内插器/ 抽取器（2），为可能的噪声不敏感变换提供控制器，该控制器被提供有通过将数字图像信号中包含的水平信号和参考水平信号进行比较而获得的控制误差信号（d） 鉴别器（4），并且控制器向校正存储器（1）提供第一致动变量（i），该第一致动变量（i）指定由该存储器执行的数字图像信号的变换，以系统定时周期的整数倍;以及 提供给内插器/抽取器（2）第二致动变量（α），其指定要由该内插器/抽取器由分数进行的变换 系统定时周期。

公开(公告)号：US5121207A

公开(公告)日：1992-06-09

申请号：US599336

申请日：1990-10-17

Applicant: Matthias Herrmann

Inventor： Matthias Herrmann

IPC: H04N5/956 ,  H04N5/073 ,  H04N9/896

CPC classification number: H04N5/0736 ,  H04N9/896

Abstract: In a digital circuit arrangement for processing an analog video signal, which operates at a fixed system clock not coupled to the video signal, in which the video signal is sampled and which comprises a correction memory (4) and an interpolator with decimator (14) which are used for converting the digital video signal to a synchronizing signal raster predetermined by the system clock, there is provided that the correction memory (4) has a predetermined number of memory sections (5, 6, 7, 8) arranged for storing each the sample values of one picture line which sample values are written or read out at the system clock, that each horizontal synchronizing pulse of the still unconverted video signal triggers a writing process of the subsequent picture line into a memory section (5, 6, 7, 8) and that each horizontal synchronizing pulse derived from the system clock triggers a reading process of the picture line that follows the previously read picture line.

Abstract translation: 在用于处理视频信号被采样并且包括校正存储器（4）和具有抽取器（14）的内插器的视频信号未被耦合的固定系统时钟的模拟视频信号的数字电路装置中， 其被用于将数字视频信号转换为由系统时钟预定的同步信号光栅，其特征在于，所述校正存储器（4）具有预定数量的存储器部分（5,6,7,8） 在系统时钟处写入或读出采样值的一个图像行的样本值，仍未转换的视频信号的每个水平同步脉冲触发后续图像行的写入处理到存储器部分（5,6,7） ，8），并且从系统时钟导出的每个水平同步脉冲触发先前读取的图像行之后的图像行的读取处理。