公开(公告)号：US11416422B2

公开(公告)日：2022-08-16

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06K7/08 ,  G06K19/06 ,  G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  G06F12/0802

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US11269780B2

公开(公告)日：2022-03-08

申请号：US16573541

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US11036593B2

公开(公告)日：2021-06-15

申请号：US16423574

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin M. Eno

IPC: G06F11/07 ,  G06F11/14 ,  G06F3/06 ,  G06F1/3225 ,  G06F11/10 ,  G06F11/16

Abstract: The present disclosure includes apparatuses and methods for performing data restore operations in memory. An embodiment includes a memory, and a controller configured to perform a data restore operation on data stored in the memory using a first table and a second table stored in the controller, wherein the first table includes a current mapping of the data stored in the memory that is based on a previous assessment of previous error rates associated with the data stored in the memory, and the second table includes a new mapping of the data stored in the memory that is based on a current assessment of current error rates associated with the data stored in the memory.

公开(公告)号：US20210149711A1

公开(公告)日：2021-05-20

申请号：US16688245

申请日：2019-11-19

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno

IPC: G06F9/48

Abstract: Systems, apparatuses, and methods to implement time to live for memory access by processors. For example, a processor has a register configured to store a parameter specifying a time duration indicative of the desired time to live. A memory system has multiple components with different latencies for memory access. When the memory controller of the processor sends a command to the memory system to load an item from a memory address, the memory system can fail to provide, to the processor within the time duration, the item from the memory address currently being hosted in a first component. In response, the memory controller can send a signal to abort the command; and the memory system can select a second component having a memory access latency shorter than the first component, and change the hosting of the memory address from in the first component to in the second component.

公开(公告)号：US20210081353A1

公开(公告)日：2021-03-18

申请号：US16573795

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Kenneth Marion Curewitz ,  Sean S. Eilert

IPC: G06F15/78 ,  G06F9/30

Abstract: An accelerator chip, e.g., an artificial intelligence (AI) accelerator chip, that can connect a system on a chip (SoC) and a memory chip. The accelerator chip can have a first set of pins configured to connect to the memory chip via wiring, as well as a second set of pins configured to connect to the SoC via wiring. The accelerator chip can be configured to perform and accelerate application-specific computations (e.g., AI computations) for the SoC, as well as use the memory chip as memory for the application-specific computations. For example, the accelerator chip can be an AI accelerator chip and the AI accelerator chip can be configured to perform and accelerate AI computations for the SoC, as well as use the memory chip as memory for the AI computations.

公开(公告)号：US20210081337A1

公开(公告)日：2021-03-18

申请号：US16573805

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth Marion Curewitz ,  Justin M. Eno

IPC: G06F13/16 ,  G06F9/30

Abstract: A memory chip (e.g., DRAM) connecting a SoC and an accelerator chip (e.g., an AI accelerator chip). A system including the memory chip and the accelerator chip. The system can include the SoC. The memory chip can include first memory cells to store and provide computation input data (e.g., AI computation input data) received from the SoC to be used by the accelerator chip as computation input (e.g., AI computation input). The memory chip can include second memory cells to store and provide first computation output data (e.g., AI computation output data) received from the accelerator chip to be retrieved by the SoC or reused by the accelerator chip as computation input. The memory chip can also include third memory cells to store second computation output data (e.g., non-AI computation output data) related to non-AI tasks received from the SoC to be retrieved by the SoC for non-AI tasks.

公开(公告)号：US20210081336A1

公开(公告)日：2021-03-18

申请号：US16573780

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivam Swami ,  Sean S. Eilert ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F13/10 ,  G06F3/06 ,  G06F12/0802 ,  G06F13/12

Abstract: A memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. The memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. The memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. Also, a system having the memory chip, the first microchip or device, and the second microchip or device.

公开(公告)号：US20190266047A1

公开(公告)日：2019-08-29

申请号：US16406775

申请日：2019-05-08

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Samuel E. Bradshaw

IPC: G06F11/10

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.

公开(公告)号：US20180285187A1

公开(公告)日：2018-10-04

申请号：US15472957

申请日：2017-03-29

Applicant: Micron Technology, Inc.

Inventor： Justin M. Eno ,  Samuel E. Bradshaw

IPC: G06F11/07

CPC classification number: G06F11/0754 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/108

Abstract: A memory device can include three-dimensional memory entities each including a plurality of two-dimensional memory entities. A controller can read data from the memory at a first resolution and collect error rate information from the memory at a second resolution including a portion of a two-dimensional memory entity. The controller can determine a quantity of two-dimensional memory entities that have a greater error rate than a remainder of the two-dimensional memory entities based on the error rate information. The controller can determine a quantity of portions of three-dimensional memory entities that have a greater error rate than a remainder of the portions of three-dimensional memory entities based on the error rate information excluding error rate information for portions of the two-dimensional memory entities associated with the quantity of two-dimensional memory entities. The controller can cull the quantity of the two-dimensional memory entities and the quantity of the three-dimensional memory entities.