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公开(公告)号：US12045503B2
公开(公告)日：2024-07-23
申请号：US17515229
申请日：2021-10-29
发明人： Kenneth Marion Curewitz , Shivam Swami , Samuel E. Bradshaw , Justin M. Eno , Ameen D. Akel , Sean S. Eilert
CPC分类号： G06F3/0659 , G06F3/0679 , G06F12/0246 , H10B63/84 , G06F3/0622
摘要： A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.
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公开(公告)号：US11768764B2
公开(公告)日：2023-09-26
申请号：US17018636
申请日：2020-09-11
发明人： Samuel E. Bradshaw , Justin Eno
IPC分类号： G06F12/02 , G06F3/06 , G06F12/1009
CPC分类号： G06F12/0246 , G06F3/0616 , G06F3/0647 , G06F3/0679 , G06F12/1009 , G06F2212/7201 , G06F2212/7211
摘要： A wear-leveling process for a memory subsystem selects a source chunk to be removed from a usable address space of the memory subsystem to distribute wear across all available chunks in the memory subsystem. The memory subsystem has a plurality of non-volatile memory components. The plurality of non-volatile memory components includes a plurality of chunks including at least one chunk in an unusable address space of the memory subsystem. The wear-leveling process copies valid data of the source chunk to a destination chunk in the unusable address space of the memory subsystem and assigns the destination chunk to a location in the usable address space of the memory subsystem occupied by the source chunk.
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公开(公告)号：US11687282B2
公开(公告)日：2023-06-27
申请号：US17236981
申请日：2021-04-21
IPC分类号： G06F3/06 , G06F12/0873 , G06F11/07
CPC分类号： G06F3/0659 , G06F3/0614 , G06F3/0653 , G06F3/0679 , G06F11/0757 , G06F12/0873
摘要： A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.
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公开(公告)号：US11664085B2
公开(公告)日：2023-05-30
申请号：US17368651
申请日：2021-07-06
发明人： Samuel E. Bradshaw , Justin Eno
CPC分类号： G11C29/70 , G06F11/1612 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/52 , G11C29/72 , G11C29/883
摘要： Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.
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公开(公告)号：US11636334B2
公开(公告)日：2023-04-25
申请号：US16545837
申请日：2019-08-20
发明人： Samuel E. Bradshaw , Shivasankar Gunasekaran , Sean Stephen Eilert , Ameen D. Akel , Kenneth Marion Curewitz
摘要： A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.
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公开(公告)号：US11455242B2
公开(公告)日：2022-09-27
申请号：US17062344
申请日：2020-10-02
发明人： Justin Eno , Samuel E. Bradshaw
摘要： A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.
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公开(公告)号：US11436041B2
公开(公告)日：2022-09-06
申请号：US16592537
申请日：2019-10-03
发明人： Dmitri Yudanov , Samuel E. Bradshaw
IPC分类号： G06F9/48 , G06F9/38 , G11C11/409 , G06F11/34 , G06F11/30
摘要： Customized root processes for groups of applications in a computing device. A computing device (e.g., a mobile device) can monitor usage of applications. The device can then store data related to the usage of the applications, and group the applications into groups according to the stored data. The device can customize and execute a root process for a group of applications according to usage common to each application in the group. The device can generate patterns of prior executions shared amongst the applications in the group based on the stored data common to each application in the group, and execute the root process of the group according to the patterns. The device can receive a request to start an application from the group from a user of the device, and start the application upon receiving the request and by using the root process of the group of applications.
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公开(公告)号：US11429445B2
公开(公告)日：2022-08-30
申请号：US16694371
申请日：2019-11-25
发明人： Dmitri Yudanov , Samuel E. Bradshaw
摘要： Enhancement or reduction of page migration can include operations that include scoring, in a computing device, each executable of at least a first group and a second group of executables in the computing device. The executables can be related to user interface elements of applications and associated with pages of memory in the computing device. For each executable, the scoring can be based at least partly on an amount of user interface elements using the executable. The first group can be located at first pages of the memory, and the second group can be located at second pages. When the scoring of the executables in the first group is higher than the scoring of the executables in the second group, the operations can include allocating or migrating the first pages to a first type of memory, and allocating or migrating the second pages to a second type of memory.
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公开(公告)号：US20220138102A1
公开(公告)日：2022-05-05
申请号：US17573938
申请日：2022-01-12
发明人： Kenneth Marion Curewitz , Ameen D. Akel , Samuel E. Bradshaw , Sean Stephen Eilert , Dmitri Yudanov
IPC分类号： G06F12/0837 , G06F12/1027 , G06F12/1009 , G06F9/38 , G06F11/14 , G06N3/02
摘要： Systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. For example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. The migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.
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公开(公告)号：US11199995B2
公开(公告)日：2021-12-14
申请号：US16688250
申请日：2019-11-19
IPC分类号： G06F3/06 , G06F12/0873 , G06F11/07
摘要： A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory subsystem can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.
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