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41.发明授权公开(公告)号：US07305524B2
公开(公告)日：2007-12-04
申请号：US10961749
申请日：2004-10-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译： 提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。 远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。 基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。
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公开(公告)号：US20120254877A1
公开(公告)日：2012-10-04
申请号：US13078263
申请日：2011-04-01
IPC分类号： G06F9/46
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.
摘要翻译： 一种用于通过在专用互连上直接在处理器核之间传输架构状态来转移架构状态绕过系统存储器的方法和装置。 传输可以由具有或不具有软件交互的状态传送接口电路来执行。 当状态传输接口电路检测到阻止正确执行与架构状态相对应的线程的错误时，线程的架构状态可以从第一处理核心传送到第二处理核心。 可以使用程序指令来启动将线程的架构状态传送到一个或多个其他线程，以通过分配多个线程的处理来并行执行线程或执行多个处理器核之间的负载平衡。
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公开(公告)号：US08949836B2
公开(公告)日：2015-02-03
申请号：US13078263
申请日：2011-04-01
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.
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公开(公告)号：US20120254548A1
公开(公告)日：2012-10-04
申请号：US13079520
申请日：2011-04-04
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0871
摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.
摘要翻译： 一种方法和装置动态地分配和释放高速缓存的一部分以用作专用本地存储。 高速缓存行可以被动态分配并被释放以包含在专用本地存储器中。 包含在专用本地存储中的缓存条目可能不会被驱逐或无效。 另外，在专用本地存储器和后备存储器中包括的缓存条目之间不保持一致性。 加载指令可以被配置为分配（例如）锁定数据高速缓存的一部分以包括在专用本地存储器中并将数据加载到专用本地存储器中。 加载指令可以被配置为从专用本地存储器读取数据并且解除分配（例如，解锁）包括在专用本地存储器中的数据高速缓存的一部分。
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公开(公告)号：US20090245257A1
公开(公告)日：2009-10-01
申请号：US12060559
申请日：2008-04-01
申请人： Miguel Comparan , Russell D. Hoover
发明人： Miguel Comparan , Russell D. Hoover
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , H04L45/60 , H04L49/109 , H04L49/25
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with all communications including a route code specifying a route through the routers of the NOC from a source to a destination, each router including routing logic that directs a communication to one of four ports of the router, the one port identified by the first two bits in the route code. The routing logic in the router shifts the route code to discard the first two bits of the route code before transmitting the communication through the one port.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），所有通信包括指定从源的路由器通过NOC的路由器的路由 到目的地，每个路由器包括将通信引导到路由器的四个端口之一的路由逻辑，由路由代码中的前两个比特标识的一个端口。 在通过一个端口发送通信之前，路由器中的路由逻辑将移动路由代码以丢弃路由代码的前两位。
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46.发明申请LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS 有权低延迟可变传输网络，用于通过多个硬件线程的虚拟螺纹的精细平行平行公开(公告)号：US20130159669A1
公开(公告)日：2013-06-20
申请号：US13330831
申请日：2011-12-20
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译： 一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。 可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得 目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。
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公开(公告)号：US09053037B2
公开(公告)日：2015-06-09
申请号：US13079520
申请日：2011-04-04
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0871
摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.
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48.发明授权公开(公告)号：US09021237B2
公开(公告)日：2015-04-28
申请号：US13330831
申请日：2011-12-20
IPC分类号： G06F9/38 , G06F15/173
CPC分类号： G06F9/3824 , G06F9/3828 , G06F9/3851 , G06F9/3891 , G06F9/544 , G06F15/173
摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.
摘要翻译： 一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。 可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得 目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。
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公开(公告)号：US08983891B2
公开(公告)日：2015-03-17
申请号：US13022881
申请日：2011-02-08
IPC分类号： G06N5/02
CPC分类号： G06N5/025
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译： 模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。 使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。 在输入流中要搜索的模式由用户定义为一组正则表达式。 要搜索的模式分组在模式上下文集中。 编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。 该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。 对于每个输入字符，PMA执行搜索并返回搜索结果。
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50.发明授权Software and hardware managed dual rule bank cache for use in a pattern matching accelerator 有权软件和硬件管理的双规则库缓存用于模式匹配加速器公开(公告)号：US08966182B2
公开(公告)日：2015-02-24
申请号：US13023058
申请日：2011-02-08
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译： 模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。 使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。 在输入流中要搜索的模式由用户定义为一组正则表达式。 要搜索的模式分组在模式上下文集中。 编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。 该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。 对于每个输入字符，PMA执行搜索并返回搜索结果。
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