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公开(公告)号：US08217953B2
公开(公告)日：2012-07-10
申请号：US12110045
申请日：2008-04-25
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/12
摘要： A circuit arrangement and method utilize texture data prefetching to prefetch texture data used by an anisotropic filtering algorithm. In particular, stride-based prefetching may be used to prefetch texture data for use in anisotropic filtering, where the value of the stride, or difference between successive accesses, is based upon a distance in a memory address space between sample points taken along the line of anisotropy used in an anisotropic filtering algorithm.
摘要翻译： 电路布置和方法利用纹理数据预取来预取由各向异性滤波算法使用的纹理数据。 特别地，可以使用基于步幅的预取来预取用于各向异性过滤中的纹理数据，其中步幅的值或连续访问之间的差是基于沿着线所取的采样点之间的存储器地址空间中的距离 在各向异性过滤算法中使用各向异性。
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公开(公告)号：US20210359672A1
公开(公告)日：2021-11-18
申请号：US16874252
申请日：2020-05-14
IPC分类号： H03K5/131 , H03K3/38 , H03K19/195 , G06N10/00 , G01R31/317
摘要： Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.
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3.发明申请公开(公告)号：US20130159799A1
公开(公告)日：2013-06-20
申请号：US13330921
申请日：2011-12-20
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/27 , G01R31/318566 , G06F11/2242
摘要： A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing.
摘要翻译： 一种方法和电路装置利用设置在多核处理器集成电路器件或芯片上的扫描逻辑来执行基于内部投票的内置自检（BIST）芯片。 测试模式在芯片内部产生，并传送到芯片上多个处理核心内的扫描链。 扫描链输出的测试结果在芯片上相互比较，多数表决用于识别表示故障处理核心的异常值测试结果。 故障测试结果中的位位置可用于识别故障处理核心中的扫描链和/或故障功能单元中的故障锁存器，并且故障处理核心和/或故障功能单元可能被自动禁用 响应测试。
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公开(公告)号：US20120254877A1
公开(公告)日：2012-10-04
申请号：US13078263
申请日：2011-04-01
IPC分类号： G06F9/46
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.
摘要翻译： 一种用于通过在专用互连上直接在处理器核之间传输架构状态来转移架构状态绕过系统存储器的方法和装置。 传输可以由具有或不具有软件交互的状态传送接口电路来执行。 当状态传输接口电路检测到阻止正确执行与架构状态相对应的线程的错误时，线程的架构状态可以从第一处理核心传送到第二处理核心。 可以使用程序指令来启动将线程的架构状态传送到一个或多个其他线程，以通过分配多个线程的处理来并行执行线程或执行多个处理器核之间的负载平衡。
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5.发明授权公开(公告)号：US08010750B2
公开(公告)日：2011-08-30
申请号：US12015975
申请日：2008-01-17
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），其中所述存储器通信控制器被配置为执行存储器访问指令并且被配置为确定 由存储器访问指令寻址的高速缓存行，高速缓存行的状态是共享，排他或无效之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。
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公开(公告)号：US11218139B2
公开(公告)日：2022-01-04
申请号：US16874252
申请日：2020-05-14
IPC分类号： G06F7/58 , H03K5/131 , H03K3/38 , G01R31/317 , G06N10/00 , H03K19/195
摘要： Ring packet built-in self-test (PBIST) circuitry configured to detect errors in wires connecting a ring of superconducting chips includes circuitry configured to make the PBIST immune to interchip latency and still allow the PBIST to test a stop-to-stop connection. By making a PBIST independent of latency, an entire ring can be characterized for latency and for its bit-error rate prior to running any functional test. Such systems and associated methods can be scaled to larger platforms having any number of ring stops. The PBIST circuitry can function as either transmitter or receiver, or both, to test an entire ring. The PBIST can also be used to tune clocks in the ring to achieve the lowest overall bit error rate (BER) in the ring.
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公开(公告)号：US08949836B2
公开(公告)日：2015-02-03
申请号：US13078263
申请日：2011-04-01
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.
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公开(公告)号：US20120254548A1
公开(公告)日：2012-10-04
申请号：US13079520
申请日：2011-04-04
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0871
摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.
摘要翻译： 一种方法和装置动态地分配和释放高速缓存的一部分以用作专用本地存储。 高速缓存行可以被动态分配并被释放以包含在专用本地存储器中。 包含在专用本地存储中的缓存条目可能不会被驱逐或无效。 另外，在专用本地存储器和后备存储器中包括的缓存条目之间不保持一致性。 加载指令可以被配置为分配（例如）锁定数据高速缓存的一部分以包括在专用本地存储器中并将数据加载到专用本地存储器中。 加载指令可以被配置为从专用本地存储器读取数据并且解除分配（例如，解锁）包括在专用本地存储器中的数据高速缓存的一部分。
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公开(公告)号：US20120144253A1
公开(公告)日：2012-06-07
申请号：US12961947
申请日：2010-12-07
CPC分类号： G06F11/0727 , G06F11/0724 , G06F11/073 , G06F11/0772
摘要： A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.
摘要翻译： 公开了一种用于管理采用锁定的存储器系统中的硬故障的技术。 内存系统中的内存单元维护错误计数。 当错误计数表示硬故障时，内存单元被锁定以供进一步使用。 分配一组任意错误计数器来记录访问内存单元所产生的错误。 本发明的实施例有利地使得即使在一个或多个内部硬盘存储器故障之后，系统也能够继续可靠的操作。 其他实施例有利地使得制造商能够回收部分故障的设备，并且将设备部署为具有较低性能规范而不是丢弃设备，否则将由常规实践指出。
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公开(公告)号：US07890699B2
公开(公告)日：2011-02-15
申请号：US11972221
申请日：2008-01-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0811
摘要： A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
摘要翻译： 在将所请求的数据返回到请求者的同时，在将所请求的数据缓存在较低级别的高速缓存中的同时，电路装置和方法将所请求的数据的存储绕过多层存储器体系结构的更高级缓存。 对于某些类型的数据，例如仅使用一次和/或很少被修改或写回存储器的数据，绕过较高级别高速缓存中的存储降低了请求的数据从较高级别投出常用数据的可能性 缓存。 然而，通过将数据缓存在较低级别的缓存中，低级缓存仍然可以窥探数据请求，并在数据已经缓存在较低级别缓存中的情况下返回请求的数据。
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