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    TRANSFERRING ARCHITECTED STATE BETWEEN CORES
    1.
    发明申请
    TRANSFERRING ARCHITECTED STATE BETWEEN CORES 有权
    转移到CORES之间的建筑状态

    公开(公告)号：US20120254877A1

    公开(公告)日：2012-10-04

    申请号：US13078263

    申请日：2011-04-01

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    IPC分类号： G06F9/46

    CPC分类号： G06F9/30043 ,  G06F9/3009 ,  G06F9/46 ,  G06F9/4856

    摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

    摘要翻译： 一种用于通过在专用互连上直接在处理器核之间传输架构状态来转移架构状态绕过系统存储器的方法和装置。 传输可以由具有或不具有软件交互的状态传送接口电路来执行。 当状态传输接口电路检测到阻止正确执行与架构状态相对应的线程的错误时，线程的架构状态可以从第一处理核心传送到第二处理核心。 可以使用程序指令来启动将线程的架构状态传送到一个或多个其他线程，以通过分配多个线程的处理来并行执行线程或执行多个处理器核之间的负载平衡。

    Network on chip that maintains cache coherency with invalidate commands
    2.
    发明授权
    Network on chip that maintains cache coherency with invalidate commands 失效
    使用无效命令维护高速缓存一致性的片上网络

    公开(公告)号：US08010750B2

    公开(公告)日：2011-08-30

    申请号：US12015975

    申请日：2008-01-17

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0833

    摘要： A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.

    摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），其中所述存储器通信控制器被配置为执行存储器访问指令并且被配置为确定 由存储器访问指令寻址的高速缓存行，高速缓存行的状态是共享，排他或无效之一; 所述存储器通信控制器被配置为如果所述高速缓存行的状态被共享，则向所述NOC的多个IP块广播无效命令; 以及所述存储器通信控制器被配置为仅当所述高速缓存行的状态是排他性时，将无效命令仅发送到控制高速缓存行存储的高速缓存的IP块。

    ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE
    4.
    发明申请
    ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE 有权
    分配缓存作为专用本地存储使用

    公开(公告)号：US20120254548A1

    公开(公告)日：2012-10-04

    申请号：US13079520

    申请日：2011-04-04

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0871

    摘要： A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage.

    摘要翻译： 一种方法和装置动态地分配和释放高速缓存的一部分以用作专用本地存储。 高速缓存行可以被动态分配并被释放以包含在专用本地存储器中。 包含在专用本地存储中的缓存条目可能不会被驱逐或无效。 另外，在专用本地存储器和后备存储器中包括的缓存条目之间不保持一致性。 加载指令可以被配置为分配（例如）锁定数据高速缓存的一部分以包括在专用本地存储器中并将数据加载到专用本地存储器中。 加载指令可以被配置为从专用本地存储器读取数据并且解除分配（例如，解锁）包括在专用本地存储器中的数据高速缓存的一部分。

    Network On Chip
    5.
    发明申请
    Network On Chip 审中-公开
    网络芯片

    公开(公告)号：US20090245257A1

    公开(公告)日：2009-10-01

    申请号：US12060559

    申请日：2008-04-01

    申请人： Miguel Comparan ,  Russell D. Hoover

    发明人： Miguel Comparan ,  Russell D. Hoover

    IPC分类号： H04L12/28

    CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/25

    摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with all communications including a route code specifying a route through the routers of the NOC from a source to a destination, each router including routing logic that directs a communication to one of four ports of the router, the one port identified by the first two bits in the route code. The routing logic in the router shifts the route code to discard the first two bits of the route code before transmitting the communication through the one port.

    摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），所有通信包括指定从源的路由器通过NOC的路由器的路由 到目的地，每个路由器包括将通信引导到路由器的四个端口之一的路由逻辑，由路由代码中的前两个比特标识的一个端口。 在通过一个端口发送通信之前，路由器中的路由逻辑将移动路由代码以丢弃路由代码的前两位。

    LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS
    6.
    发明申请
    LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS 有权
    低延迟可变传输网络，用于通过多个硬件线程的虚拟螺纹的精细平行平行

    公开(公告)号：US20130159669A1

    公开(公告)日：2013-06-20

    申请号：US13330831

    申请日：2011-12-20

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Robert A. Shearer ,  Alfred T. Watson, III

    IPC分类号： G06F15/76 ,  G06F9/02

    CPC分类号： G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/544 ,  G06F15/173

    摘要： A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

    摘要翻译： 一种方法和电路装置利用多核处理器芯片中的多个处理核心的寄存器文件之间的低延迟可变传输网络来支持跨多个硬件线程的虚拟线程的细粒度并行。 可变传输网络上的变量的通信可以通过从源处理核心的寄存器文件中的本地寄存器移动到分配给目的地处理核心中的目的地硬件线程的可变寄存器来启动，使得 目标硬件线程可以将变量从变量寄存器移动到目标处理核心中的本地寄存器。

    Network on chip that maintains cache coherency with invalidate commands
    7.
    发明授权
    Network on chip that maintains cache coherency with invalidate commands 失效
    使用无效命令维护高速缓存一致性的片上网络

    公开(公告)号：US07917703B2

    公开(公告)日：2011-03-29

    申请号：US11955553

    申请日：2007-12-13

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich ,  Alfred T. Watson, III

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich ,  Alfred T. Watson, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0837 ,  G06F15/7825

    摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.

    摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到 由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

    Network on Chip That Maintains Cache Coherency With Invalidate Commands
    8.
    发明申请
    Network on Chip That Maintains Cache Coherency With Invalidate Commands 失效
    使用无效命令维护缓存一致性的片上网络

    公开(公告)号：US20090157976A1

    公开(公告)日：2009-06-18

    申请号：US11955553

    申请日：2007-12-13

    申请人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich ,  Alfred T. Watson, III

    发明人： Miguel Comparan ,  Russell D. Hoover ,  Jamie R. Kuesel ,  Eric O. Mejdrich ,  Alfred T. Watson, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0837 ,  G06F15/7825

    摘要： A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.

    摘要翻译： 片上网络（“NOC”）通过无效命令维持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器 通信控制器和网络接口控制器，NOC还包括接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令 路由器被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。