公开(公告)号：US20220013551A1

公开(公告)日：2022-01-13

申请号：US16946842

申请日：2020-07-08

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun ,  Yuanliang Liu

IPC: H01L27/146 ,  H01L21/762

Abstract: Examples of the disclosed subject matter propose disposing trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. The trench isolation structure includes front side (e.g., shallow and deep) trench isolation structure and back side deep trench isolation structure that abut against or contacts the bottom of front side deep trench isolation structure for isolating the pixel transistor channel of the pixel cell's pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, containing, for example, a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.

公开(公告)号：US11189655B1

公开(公告)日：2021-11-30

申请号：US16946841

申请日：2020-07-08

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/761

Abstract: A pixel array is provided that addresses leaking current at or near the floating diffusion region of the pixel cells. The pixel array includes an arrangement of trench isolation structures, including both front side deep trench isolation structure and front side shallow trench isolation structure that isolate the transistor channel regions from the pixel regions (e.g., photodiodes) of the pixel array. Example embodiments also include deep (N) doped wells that extend beneath the pixel transistor regions in order to “float” the P-well regions of the pixel transistor regions.

公开(公告)号：US20210225924A1

公开(公告)日：2021-07-22

申请号：US16748657

申请日：2020-01-21

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun

IPC: H01L27/146

Abstract: A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.

公开(公告)号：US20210218914A1

公开(公告)日：2021-07-15

申请号：US16738981

申请日：2020-01-09

Applicant: OmniVision Technologies, Inc.

Inventor： Seong Yeol Mun

IPC: H04N5/361 ,  H01L27/146 ,  H01L29/51 ,  H04N5/378

Abstract: A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

公开(公告)号：US20210202552A1

公开(公告)日：2021-07-01

申请号：US16729163

申请日：2019-12-27

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Seong Yeol Mun ,  Young Woo Jung

IPC: H01L27/146

Abstract: Image sensors include a photodiode formed in a substrate material and a transistor coupled to the photodiode. The transistor has a trench structure formed in the substrate material, an isolation layer disposed on the substrate material, and a gate disposed on the isolation layer and extending into the trench structure. The trench structure has a polygonal cross section in a channel width plane, the polygonal cross section defining at least four sidewall portions of the substrate material, which contribute to an effective channel width measured in the channel width plane that is wider than a planar channel width of the transistor.