公开(公告)号：US5258951A

公开(公告)日：1993-11-02

申请号：US919428

申请日：1992-07-27

申请人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

发明人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/062 ,  G11C7/1051

摘要： A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

摘要翻译： 存储器（20）具有读周期和写周期。 在读周期期间，对应于由所选存储单元提供的数据的差分数据信号叠加在第一共模电压上并提供给数据输出缓冲器（70-73）。 在写周期期间，读取全局数据线（61-62）上的差分数据信号在第二共模电压下相等，数据输出缓冲器（70-73）被禁用。 输出使能电路（74）在第一和第二共模电压之间提供输出使能信号。 当差分数据信号从第二共模电压转换到第一共模电压时，差分数据信号与输出使能信号交叉时，数据输出缓冲器（70-73）在读周期开始时使能。 以这种方式启用数据输出缓冲器（70-73）可大大放宽输出使能时序约束。