公开(公告)号：US5258951A

公开(公告)日：1993-11-02

申请号：US919428

申请日：1992-07-27

申请人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

发明人： Ruey J. Yu ,  Kenneth W. Jones ,  Ray Chang ,  Karl Wang

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/062 ,  G11C7/1051

摘要： A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

摘要翻译： 存储器（20）具有读周期和写周期。 在读周期期间，对应于由所选存储单元提供的数据的差分数据信号叠加在第一共模电压上并提供给数据输出缓冲器（70-73）。 在写周期期间，读取全局数据线（61-62）上的差分数据信号在第二共模电压下相等，数据输出缓冲器（70-73）被禁用。 输出使能电路（74）在第一和第二共模电压之间提供输出使能信号。 当差分数据信号从第二共模电压转换到第一共模电压时，差分数据信号与输出使能信号交叉时，数据输出缓冲器（70-73）在读周期开始时使能。 以这种方式启用数据输出缓冲器（70-73）可大大放宽输出使能时序约束。

公开(公告)号：US5610543A

公开(公告)日：1997-03-11

申请号：US417155

申请日：1995-04-04

申请人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

发明人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

IPC分类号： G11C7/22 ,  H03L7/06 ,  H03K5/13

CPC分类号： G11C7/22

摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

摘要翻译： 延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。 仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步， 。 塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。 延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

公开(公告)号：US5422848A

公开(公告)日：1995-06-06

申请号：US909484

申请日：1992-07-06

申请人： Kenneth W. Jones ,  Ray Chang

发明人： Kenneth W. Jones ,  Ray Chang

IPC分类号： G11C7/22 ,  H03K19/0175 ,  G11C7/00 ,  H03K19/094

CPC分类号： H03K19/017527 ,  G11C7/22

摘要： An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.

摘要翻译： 具有单面延迟的ECL至CMOS缓冲器包括ECL逻辑门，电平转换器，多个串联连接的反相器和NOR门。 ECL逻辑门接收ECL电平输入信号，并提供互补的中间电平逻辑信号。 电平转换器接收中间电平逻辑信号并提供CMOS电平输出信号。 NOR门通过串联连接的反相器在预定的延迟之后的输入端接收CMOS电平输出信号。 中间电平逻辑信号之一也由第二输入端上的或非门接收。 CMOS电平输出信号在低到高的转换期间被延迟预定的时间，在高到低的转变中没有不期望的延迟。

公开(公告)号：US5268863A

公开(公告)日：1993-12-07

申请号：US909485

申请日：1992-07-06

申请人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

发明人： Mark D. Bader ,  Kenneth W. Jones ,  Karl L. Wang ,  Ray Chang

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

公开(公告)号：US5477176A

公开(公告)日：1995-12-19

申请号：US253076

申请日：1994-06-02

申请人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

发明人： Ray Chang ,  Lawrence F. Childs ,  Kenneth W. Jones ,  Donovan Raatz ,  Stephen Flannagan

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C8/10 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  G11C5/143 ,  G11C8/10 ,  H03K17/22 ,  H03K2017/226

摘要： A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

摘要翻译： 用于存储器（20）的上电复位电路（30）包括DC模型电路（39），NBIAS校验电路（64）和NAND逻辑门（71）。 在存储器（20）的上电时提供逻辑低电源复位信号，以在时钟电路（29）和行和列预解码器/锁存器（24,27）中建立初始条件。 当电源电压，带隙参考电压和偏置电压都达到其预定电压时，上电复位电路（30）提供逻辑高的上电复位信号。 以这种方式，确保上电复位电路（30）提供逻辑低功率复位信号，直到达到所有适当的电压电平。 此外，上电复位电路为等效于地址缓冲电路（79）的DC电路建模，用于补偿过程和温度变化。

公开(公告)号：US5440515A

公开(公告)日：1995-08-08

申请号：US207517

申请日：1994-03-08

申请人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

发明人： Ray Chang ,  Stephen T. Flannagan ,  Kenneth W. Jones

IPC分类号： G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22

摘要： A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

摘要翻译： 延迟锁定环路（44）包括仲裁器电路（86），VCD电路（85）和崩溃检测器（88）。 仲裁器电路（86）接收输入信号并提供延迟信号以调整VCD电路（85）的传播延迟量，以使输入信号的相位与VCD电路（85）的输出信号同步， 。 塌陷检测器（88）检测VCD电路（85）的输出信号是否在预定的时间长度内不能改变逻辑状态。 延迟锁定环路（44）可锁定具有不同频率的两个信号的相位。

公开(公告)号：US5384737A

公开(公告)日：1995-01-24

申请号：US207509

申请日：1994-03-08

申请人： Lawrence F. Childs ,  Kenneth W. Jones ,  Stephen T. Flannagan ,  Ray Chang

发明人： Lawrence F. Childs ,  Kenneth W. Jones ,  Stephen T. Flannagan ,  Ray Chang

IPC分类号： G11C7/10 ,  G11C29/14 ,  G11C13/00

CPC分类号： G11C29/14 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1072

摘要： A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

摘要翻译： 流水线存储器（20）具有同步操作模式和异步操作模式。 存储器（20）包括用于在异步操作模式和同步操作模式之间电切换的输出寄存器（34）和输出使能寄存器（48）。 另外，在同步运行模式中，流水线的深度可以在三段管线和两级管线之间变化。 通过改变流水线的深度，存储器（20）可以使用更大的时钟频率范围来操作。 另外，可以改变操作频率以便于存储器（20）的测试和调试。

公开(公告)号：US5400274A

公开(公告)日：1995-03-21

申请号：US236845

申请日：1994-05-02

申请人： Kenneth W. Jones ,  Lawrence F. Childs

发明人： Kenneth W. Jones ,  Lawrence F. Childs

IPC分类号： G11C7/10 ,  G11C5/06

CPC分类号： G11C7/10

摘要： A synchronous memory (50) having a looped global data line (80) reduces a difference between minimum and maximum propagation delays between different locations in a memory array (51) during a read cycle of the memory (50). The looped global data line (80) has a first portion (80') and a second portion (80"). The first portion (80') extends along an edge of the memory array (51) in a direction substantially parallel to a direction of the word lines of the array (51). Sense amplifiers (73-78) are coupled to the first portion (80') of the looped global data line (80). At one end of the array (51), the second portion (80") of the looped global data line extends back in an opposite direction to the first portion (80') and is coupled to output data circuits (84). Reducing the difference in propagation delays improves noise margins and allows increased operating speed.

摘要翻译： 具有循环全局数据线（80）的同步存储器（50）在存储器（50）的读取周期期间减少存储器阵列（51）中的不同位置之间的最小和最大传播延迟之间的差异。 环路全局数据线（80）具有第一部分（80'）和第二部分（80“）。 第一部分（80'）沿着与阵列（51）的字线的方向基本平行的方向沿着存储器阵列（51）的边缘延伸。 感测放大器（73-78）耦合到环路全局数据线（80）的第一部分（80'）。 在阵列（51）的一端，环形全局数据线的第二部分（80“）在与第一部分（80'）相反的方向上延伸并耦合到输出数据电路（84）。 降低传播延迟的差异可以提高噪音容限，并提高运行速度。

公开(公告)号：US5217592A

公开(公告)日：1993-06-08

申请号：US696316

申请日：1991-04-30

申请人： Kenneth W. Jones

发明人： Kenneth W. Jones

IPC分类号： B01D57/02 ,  G01N27/447

CPC分类号： B01D57/02 ,  G01N27/44717

摘要： An apparatus which includes the combination of a submarine gel tank, for the electrophoresic separation of, for example, nucleic acid molecules on agarose slab gels, with a vacuum applying means which transfers the separated molecules from the gel, without further handling, to a filter membrane by means of a controlled vacuum.

摘要翻译： 一种装置，其包括用于电泳分离琼脂糖凝胶上的核酸分子的潜艇凝胶罐与真空施加装置的组合，所述真空施加装置将分离出的分子从凝胶转移而不进一步处理到过滤器 膜通过受控真空。

公开(公告)号：US4846290A

公开(公告)日：1989-07-11

申请号：US207684

申请日：1988-06-16

申请人： Kenneth W. Jones

发明人： Kenneth W. Jones

IPC分类号： E21B10/12 ,  E21B10/22 ,  E21B10/34 ,  E21B10/50 ,  E21B10/52 ,  E21B10/56 ,  E21B10/567 ,  E21B10/62

CPC分类号： E21B10/52 ,  E21B10/12 ,  E21B10/22 ,  E21B10/34 ,  E21B10/50 ,  E21B10/567 ,  E21B10/62

摘要： A sub-surface borehole underreamer is disclosed having freely rotatable precessing diamond cutters attached to extendable arms connected to the body of the underreamer. The diamond cutting face is skewed to a degree that tangential contact of the peripheral edge of the diamond cutter causes the rotating cutter to precess as the underreamer body is rotated by a drill string.

摘要翻译： 公开了一种子表面钻孔扩孔器，其具有可自由旋转的进给金刚石切割器，该切割器附接到连接到扩孔器主体的可伸缩臂。 金刚石切割面歪斜到金刚石切割器的周缘的切向接触使得旋转切割器在钻头主体被钻柱旋转时进入。