公开(公告)号：US12125551B2

公开(公告)日：2024-10-22

申请号：US17874973

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ku-Feng Lin ,  Hiroki Noguchi

IPC分类号： G11C16/04 ,  G11C7/06 ,  G11C11/16 ,  G11C13/00

CPC分类号： G11C7/062 ,  G11C11/16 ,  G11C13/004

摘要： A memory device includes a plurality of sense amplifiers, a plurality of memory cells, a plurality of data lines, a plurality of reference cells, and a connection line. The memory cells are coupled to a plurality of first inputs of the plurality of sense amplifiers respectively. The data lines are coupled to a plurality of second inputs of the plurality of sense amplifiers respectively. The reference cells are arranged in a plurality of columns respectively and coupled to the plurality of data line respectively. Each of the plurality of reference cells includes a plurality of resistive elements. The connection line is coupled to the plurality of data lines. In a read mode, one of the sense amplifiers is configured to access the plurality of resistive elements arranged in at least one of the plurality of columns.

公开(公告)号：US12087389B2

公开(公告)日：2024-09-10

申请号：US17874534

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jaw-Juinn Horng ,  Chin-Ho Chang ,  Yung-Chow Peng ,  Szu-Chun Tsao

IPC分类号： G11C7/10 ,  G06F7/544 ,  G11C7/06 ,  H03M1/46

CPC分类号： G11C7/1057 ,  G06F7/5443 ,  G11C7/062 ,  G11C7/1084 ,  H03M1/462

摘要： In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

公开(公告)号：US11961580B2

公开(公告)日：2024-04-16

申请号：US17805026

申请日：2022-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Che Lu ,  Chin-Ming Fu ,  Chih-Hsien Chang

IPC分类号： G11C7/06 ,  G11C5/14 ,  G11C7/10 ,  G11C7/14

CPC分类号： G11C7/062 ,  G11C5/14 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/14

摘要： A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.

公开(公告)号：US11948657B2

公开(公告)日：2024-04-02

申请号：US17547574

申请日：2021-12-10

申请人： Micron Technology, Inc.

发明人： Christopher G. Wieduwilt ,  Eric J. Schultz

IPC分类号： G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  H01L27/088 ,  G06F30/392

CPC分类号： G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H01L27/0886 ,  G06F30/392

摘要： Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.

公开(公告)号：US11862285B2

公开(公告)日：2024-01-02

申请号：US17474166

申请日：2021-09-14

申请人： ANHUI UNIVERSITY ,  CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Zhiting Lin ,  Jianqing Li ,  Jun He ,  Zhan Ying ,  Xin Li ,  Kanyu Cao ,  Wenjuan Lu ,  Chunyu Peng ,  Xiulong Wu ,  Junning Chen

IPC分类号： G11C7/08 ,  G11C7/12 ,  G11C7/06

CPC分类号： G11C7/08 ,  G11C7/062 ,  G11C7/12

摘要： A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

公开(公告)号：US11783872B2

公开(公告)日：2023-10-10

申请号：US17555076

申请日：2021-12-17

申请人： Micron Technology, Inc.

发明人： Glen E. Hush ,  Honglin Sun ,  Richard C. Murphy

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C7/08 ,  G11C13/00 ,  G06N3/063

CPC分类号： G11C7/065 ,  G06N3/063 ,  G11C7/062 ,  G11C7/08 ,  G11C11/4091 ,  G11C2013/0054

摘要： Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amplifiers of the memory device. For example, those sense amplifiers, among the plurality of sense amplifiers, storing data associated with the operation(s) can be determined, and the data can be selectively sent from the determined sense amplifiers to an operation unit, in which the operations are performed. The operations may be made without affecting a subsequent read command that requests data from the plurality of sense amplifiers.

公开(公告)号：US11742012B2

公开(公告)日：2023-08-29

申请号：US17333109

申请日：2021-05-28

申请人： NXP USA, INC.

发明人： Karthik Ramanan ,  Jon Scott Choy ,  Padmaraj Sanjeevarao

IPC分类号： G11C11/16 ,  G11C7/06 ,  G11C7/08 ,  G11C11/4074 ,  G11C13/00

CPC分类号： G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C11/4074 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2013/0054

摘要： A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

公开(公告)号：US20190096465A1

公开(公告)日：2019-03-28

申请号：US16184719

申请日：2018-11-08

申请人： Micron Technology, Inc.

发明人： Giulio Giuseppe Marotta ,  Marco Domenico Tiburzi

IPC分类号： G11C11/22 ,  G11C11/56

CPC分类号： G11C11/2273 ,  G11C7/062 ,  G11C7/067 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/5657 ,  G11C2213/77

摘要： Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual ground circuitry operably coupled to the sense circuit. The virtual ground circuitry is configured to provide a virtual ground at a first bias voltage potential to a conductive line operably coupled to a selected ferroelectric memory cell, and discharge the conductive line to the sense node responsive to the selected ferroelectric memory cell changing from a first polarization state to a second polarization state. A method includes applying a second bias voltage potential to another conductive line operably coupled to the selected ferroelectric memory cell, and comparing a sense node voltage potential to a reference voltage potential. Electrical systems and computing devices include virtual ground sensing circuits.

公开(公告)号：US20190066783A1

公开(公告)日：2019-02-28

申请号：US16176390

申请日：2018-10-31

申请人： Micron Technology, Inc.

发明人： Makoto Kitagawa ,  Kerry Tedrow

IPC分类号： G11C13/00 ,  G11C7/06 ,  G11C11/56

CPC分类号： G11C13/0064 ,  G11C7/062 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

摘要： Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

公开(公告)号：US20190013053A1

公开(公告)日：2019-01-10

申请号：US16008042

申请日：2018-06-14

申请人： Winbond Electronics Corp.

发明人： Hung-Hsueh Lin

IPC分类号： G11C7/12 ,  G11C7/06 ,  G11C16/26

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/062 ,  G11C16/24 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/063

摘要： A current-sensing circuit for a memory and a sensing method thereof are provided. The current-sensing circuit includes a pre-charge circuit, a sensing current-to-voltage generator, an auxiliary current-to-voltage generator, a reference current-to-voltage generator, and a detection circuit. The pre-charge circuit provides a pre-charge signal to a selected bit line during a pre-charge time period. The sensing current-to-voltage generator generates a sensing voltage to a memory cell current of the selected bit line via a first load. The auxiliary current-to-voltage generator provides a detection voltage to a portion of the memory cell current of the selected bit line via a second load. The reference current-to-voltage generator provides a reference voltage during a data-sensing time period. The detection circuit determines an end time point of the pre-charge time period by comparing a detected voltage generated by the second load with a reference voltage.