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44 条记录 (耗时 0.019 秒)

    Basic cell for programmable analog time-continuous filter
    41.
    发明授权
    Basic cell for programmable analog time-continuous filter 失效
    可编程模拟时间连续滤波器的基本单元

    公开(公告)号：US06359503B1

    公开(公告)日：2002-03-19

    申请号：US08999962

    申请日：1997-08-12

    申请人： Roberto Alini ,  Francesco Brianti ,  Valerio Pisati ,  Marco Demicheli

    发明人： Roberto Alini ,  Francesco Brianti ,  Valerio Pisati ,  Marco Demicheli

    IPC分类号： H03K500

    CPC分类号： H03H15/00 ,  H02P6/21 ,  H03H11/0422

    摘要： An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node. “Elementary cell structure for programmable time-continuous analog filters and in particular for read/write operations on magnetic supports and associated analog filter”

    摘要翻译： 用于可编程时间连续模拟滤波器的基本单元结构，特别是用于在磁性支撑上的读取/写入操作中处理模拟信号的基本单元结构包括：放大器级，其设置有一对在公共电路节点中连接在一起的结构相同的跨导半电池 。 这种类型的单元级联提供了一种时间连续的模拟延迟线，其用于横向时间连续的模拟滤波器。 该滤波器包括通过乘法器节点连接到最终求和节点的相同延迟线级联。 “用于可编程时间连续模拟滤波器的基本单元结构，特别是用于磁性支持和相关模拟滤波器的读/写操作”

    Pipelined decoder for high frequency operation
    44.
    发明授权
    Pipelined decoder for high frequency operation 失效
    流水线解码器，用于高频操作

    公开(公告)号：US5528237A

    公开(公告)日：1996-06-18

    申请号：US285918

    申请日：1994-08-03

    申请人： David Moloney ,  Paolo Gadducci ,  Giorgio Betti ,  Roberto Alini

    发明人： David Moloney ,  Paolo Gadducci ,  Giorgio Betti ,  Roberto Alini

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14 ,  H03M7/00

    CPC分类号： H03M5/145 ,  G11B20/1426

    摘要： A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the rising front of the output sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating speed may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

    摘要翻译： 用于解码串行数据流的解码器采用提取的基本时钟信号，与输入，编码的串行数据流同步，用于对解码的输出数据流进行采样的第一分数次频率时钟信号和用于合成预 由第一组合逻辑网络产生的解码值在第二组合逻辑网络内，以产生被发送到输出采样触发器的解码值。 在根据本发明的解码器中，通过暂时存储在第二组合逻辑网络中处理的比特（由解码器处理的一部分比特）并通过预测同步基准时钟的两个完整周期来实现流水线操作 通过所述第一组合网络处理由解码器处理的总共n个比特的比特的信号。 允许两个组合逻辑网络中的每一个在输出采样时钟信号的上升沿之前的整个时钟周期内完成其解码处理。 使用相同的制造技术，因此具有相同的两个组合逻辑网络的传播延迟，最大的操作速度可以加倍。 需要有限数量的附加部件来实现本发明的流水线操作。