Data processing apparatus, and data processing method

    公开(公告)号:US10789165B2

    公开(公告)日:2020-09-29

    申请号:US15754331

    申请日:2016-10-27

    Inventor: Makiko Yamamoto

    Abstract: The present technique relates to a data processing apparatus, and a data processing method each of which enables a valid address to be more reliably produced in interleave. In a data processing apparatus, a frequency interleaver for carrying out frequency interleave calculates a first bit stream produced by a first pseudo random number generating portion configured to produce a random bit stream, a second bit stream produced by a second pseudo random number generating portion configured to produce a random bit stream, and an additional bit produced by a bit producing portion configured to alternately produce a bit as 0 and a bit as 1. As a result, in producing a write address or a read address including a random bit stream, the bit as 0 and the bit as 1 are alternately repeated as the most, significant bit in the random bit stream. The present technique, for example, can be applied to a frequency interleaver for carrying out frequency interleave.

    Data processing apparatus and data processing method

    公开(公告)号:US10530389B2

    公开(公告)日:2020-01-07

    申请号:US15935760

    申请日:2018-03-26

    Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance.An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

    Data processing device and data processing method

    公开(公告)号:US10411741B2

    公开(公告)日:2019-09-10

    申请号:US15993269

    申请日:2018-05-30

    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

    Data processing device and data processing method

    公开(公告)号:US10320416B2

    公开(公告)日:2019-06-11

    申请号:US15935951

    申请日:2018-03-26

    Abstract: The present technology relates to a data processing device and a data processing method so that an LDPC code with a good bit error rate is provided.An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 8/15. The LDPC code includes information bits and parity bits. A parity check matrix H includes an information matrix part corresponding to the information bits of the LDPC code and a parity matrix part corresponding to the parity bits. The information matrix part of the parity check matrix H is represented by a parity check matrix initial value table that indicates a position of an element 1 of the information matrix part for each 360 columns. The present technology is applicable to a case in which LDPC encoding and LDPC decoding are performed.

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