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    Data processing apparatus and data processing method
    1.
    发明授权
    Data processing apparatus and data processing method 有权

    公开(公告)号：US11177832B2

    公开(公告)日：2021-11-16

    申请号：US16696746

    申请日：2019-11-26

    Applicant: Saturn Licensing LLC

    Inventor： Yuji Shinohara ,  Makiko Yamamoto

    IPC: H03M13/11 ,  H03M13/27 ,  H03M13/35 ,  H04L1/00 ,  H03M13/03 ,  H03M13/25 ,  H03M13/29 ,  H03M13/15

    Abstract: The present technology relates to a data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance.
    An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology may be applied to LDPC encoding and LDPC decoding.

    Data processing device and data processing method
    3.
    发明授权
    Data processing device and data processing method 有权

    公开(公告)号：US10985782B2

    公开(公告)日：2021-04-20

    申请号：US16459088

    申请日：2019-07-01

    Applicant: SATURN LICENSING LLC

    Inventor： Ryoji Ikegaya ,  Makiko Yamamoto ,  Yuji Shinohara

    IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M13/15

    Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes.
    In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    4.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：US20200304152A1

    公开(公告)日：2020-09-24

    申请号：US16839813

    申请日：2020-04-03

    Applicant: Saturn Licensing LLC

    Inventor： Ryoji IKEGAYA ,  Makiko Yamamoto ,  Yuji Shinohara

    IPC: H03M13/27 ,  H03M13/03 ,  H03M13/11 ,  H03M13/29 ,  H03M13/35 ,  H03M13/00 ,  H03M13/25

    Abstract: The present technology relates to a data processing device and a data processing method capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of LDPC codes after the group-wise interleave is returned to an original sequence. The present technology, for example, can be applied to a case where data transmission using an LDPC code or the like is performed.

    Data processing apparatus, and data processing method
    9.
    发明授权
    Data processing apparatus, and data processing method 有权

    公开(公告)号：US11341047B2

    公开(公告)日：2022-05-24

    申请号：US16997669

    申请日：2020-08-19

    Applicant: Saturn Licensing LLC

    Inventor： Makiko Yamamoto

    IPC: G06F12/06 ,  H03M13/27 ,  G06F7/58 ,  H04L1/00 ,  H04L27/26

    Abstract: A data processing apparatus including a frequency interleaves that includes memory configured to write and read data, and an address generator configured to produce a write address and a read address, and that writes the data to the memory in accordance with the write address and reads out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving. The address generator is configured to produce a first pseudo random bit stream, produce a second pseudo random bit stream, alternately produce a bit as 0 and a bit as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

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