公开(公告)号：US20180341594A1

公开(公告)日：2018-11-29

申请号：US15606502

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US10140027B1

公开(公告)日：2018-11-27

申请号：US15606549

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F1/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.