公开(公告)号：US20050174145A1

公开(公告)日：2005-08-11

申请号：US10513965

申请日：2003-08-27

申请人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

发明人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

IPC分类号： G09G3/36 ,  H04L25/02 ,  H04L25/49 ,  H03K19/094

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2330/06 ,  H04L25/0272 ,  H04L25/4902

摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

摘要翻译： 在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度被时钟传输系统（12）反馈控制，从而传输时钟信号 在一个小幅度。 具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。 此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。