公开(公告)号：US10003342B2

公开(公告)日：2018-06-19

申请号：US14740499

申请日：2015-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Lin Liu ,  Lee-Chung Lu ,  Meng-Hsueh Wang ,  Shang-Chih Hsieh ,  Henry Huang ,  Ji-Yung Lin

IPC: H03K19/21

CPC classification number: H03K19/21

Abstract: A compressor circuit includes a plurality of inputs, a sum output, and a plurality of XOR circuits. Each XOR circuit of the plurality of XOR circuits includes first, second and third inputs, and a first output. The XOR circuit is configured to generate a logic value A⊕B⊕C at the first output, where A, B and C are logic values at the corresponding first, second and third inputs, and “⊕” is the XOR logic operation. The plurality of XOR circuits includes first and second XOR circuits. The first, second and third inputs of the first XOR circuit are coupled to corresponding inputs among the plurality of inputs of the compressor circuit. The first output of the first XOR circuit is coupled to the first input of the second XOR circuit. The first output of the second XOR circuit is coupled to the sum output.