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公开(公告)号：US20190221288A1
公开(公告)日：2019-07-18
申请号：US16302542
申请日：2017-05-16
CPC分类号： G16B30/00 , G06F5/01 , G06F13/1668 , G06F13/4282 , G06F15/7821 , G06F2213/0026 , G06F2213/0042 , G11C7/1006 , G11C7/1036 , G11C11/41 , G11C19/00 , G11C19/184 , G11C19/287 , H03K19/21
摘要： A computer system and method for sequencing deoxyribonucleic acid (DNA), to determine the order of the different nucleotides in a genomic sequence or sequence fragment. An alignment system employs a direct “brute force” Hamming distance calculation between a read sequence and a reference genome. The alignment system is configured to compare directly a set of DNA fragments to a reference genome in a short period, and with the higher probability of accuracy than similar comparison systems given the same number of clock cycles. Each DNA fragment is compared with a reference genome for the entire length of the latter using arrangements of memory cells for storing read sequences and inverse complements of the read sequences, shift registers for streaming the reference genome, and circuitry for calculating and summing the distance between the reference, the read sequence, and the inverse complement in parallel. Both digital and analog implementations are described.
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公开(公告)号：US20180302067A1
公开(公告)日：2018-10-18
申请号：US15933021
申请日：2018-03-22
CPC分类号： H03K5/01 , G06F1/12 , H03K3/037 , H03K3/0375 , H03K5/15046 , H03K5/15066 , H03K19/21 , H03K2005/00078
摘要： A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
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公开(公告)号：US20180278251A1
公开(公告)日：2018-09-27
申请号：US15926703
申请日：2018-03-20
申请人： Synaptics Japan GK
发明人： Tsuyoshi KUROIWA
CPC分类号： H03K19/00346 , H03K3/037 , H03K3/12 , H03K5/05 , H03K5/13 , H03K19/20 , H03K19/21 , H04B1/04 , H04B1/16
摘要： A system and method for digital signal reception comprise outputting first and second digital transmission signals complementary to each other. Further, a first and second output signals are outputted. The first output signal has a logical value based on a product of a logical value of the first digital transmission signal and a logical value complementary to a logical value of the second digital transmission signal is outputted. The second output signal has a logical value based on a sum of a logical value complementary to the logical value of the first digital transmission signal and the logical value of the second digital transmission signal.
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公开(公告)号：US20180196641A1
公开(公告)日：2018-07-12
申请号：US15866237
申请日：2018-01-09
发明人： Takeshi Aoyagi
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84 , H03K19/21
摘要： A random, number generating apparatus includes a first ring oscillator and a second ring oscillator, each having a quantity of delay elements different from, the other, a signal output unit, a selecting unit, a logic circuit, and a random signal output unit. The signal output unit receives a first signal output from the first ring oscillator and a second signal output from, the second ring oscillator and outputs the first signal or the second signal. The selecting unit selects a signal to be output from the signal output unit. The logic circuit receives the signal selected by the selecting unit and the output from the signal output unit and outputs an output signal. The random signal output unit receives the output signal output from the logic circuit and a clock signal and outputs a random signal.
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公开(公告)号：US10014849B2
公开(公告)日：2018-07-03
申请号：US15440339
申请日：2017-02-23
申请人： SK hynix Inc.
发明人： Hyunjin Noh
IPC分类号： H03K5/1534 , H03K5/135 , H03K19/21 , G06F11/07
CPC分类号： H03K5/1534 , G06F11/0706 , G06F11/0751 , H03K5/135 , H03K19/21
摘要： A clock detector a first delay circuit delaying an input clock by a first delay time and outputting the delayed input clock as a delayed clock signal, an edge detection circuit receiving the input clock and the delayed clock signal to generate an output signal including pulses which are created in synchronization with edges of the input clock, a delay/inversion circuit delaying the output signal of the edge detection circuit by a second delay time and inverting the delayed output signal to output the inverted signal as an output signal, a first flip-flop receiving the input clock to generate a first output signal, a second flip-flop receiving the first output signal to generate a second output signal, and a clock detection signal generation circuit receiving the first and second output signals to generate a clock detection signal.
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公开(公告)号：US20180159538A1
公开(公告)日：2018-06-07
申请号：US15607588
申请日：2017-05-29
IPC分类号： H03K19/21
CPC分类号： H03K19/21 , G08C2201/91 , H03K19/1733 , H03K19/1737 , H03K2217/94021 , H04L61/2038 , H04L61/6072
摘要： A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.
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公开(公告)号：US09973332B2
公开(公告)日：2018-05-15
申请号：US15413434
申请日：2017-01-24
发明人： Hong-Yean Hsieh
IPC分类号： H04L7/02 , H03K5/135 , H03L7/091 , H03L7/08 , H03K19/21 , H03L7/093 , H03L7/107 , H03L7/18 , H03K5/00
CPC分类号： H04L7/02 , H03K5/135 , H03K19/21 , H03K2005/00052 , H03L7/0807 , H03L7/091 , H03L7/093 , H03L7/1075 , H03L7/18 , H03L2207/50
摘要： An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.
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公开(公告)号：US09966953B2
公开(公告)日：2018-05-08
申请号：US15171487
申请日：2016-06-02
发明人： Qi Ye , Animesh Datta , Bo Pang
CPC分类号： H03K19/0016 , H03K3/012 , H03K3/037 , H03K19/21
摘要： A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.
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公开(公告)号：US20180083809A1
公开(公告)日：2018-03-22
申请号：US15602080
申请日：2017-05-22
申请人： KANDOU LABS, S.A.
发明人： Armin Tajalli , Ali Hormati
CPC分类号： H03L7/0807 , H03K19/21 , H03L7/087 , H03L7/0891 , H03L7/0995 , H03L7/0998 , H03L2207/06 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L25/493 , H04L2203/02
摘要： Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.
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公开(公告)号：US20180067725A1
公开(公告)日：2018-03-08
申请号：US15697370
申请日：2017-09-06
申请人： Bertrand Cambou
发明人： Bertrand Cambou
摘要： Implementations of data compilers may include: a physical device including a physical parameter, the physical parameter including at least three states. The data compiler may also include a data stream generated from the physical parameter. The data stream may include a plurality of bits. Each bit may be coded with one of a 0, a 1, and an X; the 0, the 1, and the X may correspond with one of the at least three states of the physical parameter, respectively. The data compiler may also include an exclusive OR (XOR) data processor. The XOR processor may be configured to randomize the at least three states of the data stream and output a randomized output data stream.
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