公开(公告)号：US20110243319A1

公开(公告)日：2011-10-06

申请号：US12812903

申请日：2009-01-21

申请人： Taizo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

发明人： Taizo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

IPC分类号： H04L9/28

CPC分类号： H04L9/28 ,  G09C1/00 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/122

摘要： A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments.

摘要翻译： 实现了实现有效数据扩散的数据转换算法。 例如，在将包含排列1字节的数据块的数据的矩形矩阵分割成两部分进行数据转换的两个数据段执行各种处理的结构中，实现了以较少的运算成本的有效数据加扰 通过对数据段之一执行线性转换处理，在两个数据段之间进行异或运算，对数据段之一进行移位处理，以及两个数据段之间的交换处理。 此外，通过在数据段上包括非线性转换或密钥应用操作来实现具有高安全级别的密码处理。

公开(公告)号：US20110211688A1

公开(公告)日：2011-09-01

申请号：US13059641

申请日：2009-08-25

申请人： Taizo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

发明人： Taizo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

IPC分类号： H04L9/28 ,  H04K1/04

CPC分类号： H04L9/0643 ,  H04L9/0637 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/30

摘要： A construction with an improved compression-function execution section is achieved. A data conversion process with use of a plurality of compression-function execution sections and through a plurality of process sequences in which divided data blocks constituting message data are processed in parallel is executed. Each of the plurality of compression-function execution sections performs a process with use of a message scheduling section which receives a corresponding divided data block of the message data to perform a message scheduling process, and a process with use of a chaining variable processing section which receives both of an output from the message scheduling section and an intermediate value as an output from a preceding processing section to generate output data whose number of bits is same as that of the intermediate value through compression of received data. The plurality of compression-function execution sections, respectively performing parallel processing commonly use one or both of the message scheduling section and the chaining variable processing section, and allow a single message scheduling section or a single chaining variable processing section to be utilized. Downsizing of a hardware configuration and simplification of processing steps are achieved by such a construction.

摘要翻译： 实现了具有改进的压缩函数执行部分的结构。 执行使用多个压缩函数执行部分并且通过并行处理构成消息数据的划分数据块的多个处理序列的数据转换处理。 多个压缩函数执行部中的每一个执行使用消息调度部的处理，该消息调度部接收消息数据的对应的分割数据块来执行消息调度处理，以及使用链接变量处理部的处理 接收来自消息调度部分的输出和来自前一处理部分的输出的中间值，以通过压缩接收到的数据来产生其数目与中间值的位数相同的输出数据。 分别执行并行处理的多个压缩函数执行部分通常使用消息调度部分和链接变量处理部分中的一个或两个，并且允许使用单个消息调度部分或单个链接变量处理部分。 通过这种结构实现了硬件配置的小型化和处理步骤的简化。

公开(公告)号：US09350051B2

公开(公告)日：2016-05-24

申请号：US13988162

申请日：2011-11-17

申请人： Shigeki Teramoto ,  Shinichi Uesaka ,  Atsushi Ozawa ,  Kazuo Nakamura ,  Asami Yoshida ,  Toru Akishita ,  Shiho Moriai

发明人： Shigeki Teramoto ,  Shinichi Uesaka ,  Atsushi Ozawa ,  Kazuo Nakamura ,  Asami Yoshida ,  Toru Akishita ,  Shiho Moriai

IPC分类号： H01M14/00 ,  H01M10/42 ,  H01M10/04 ,  H01M10/48

CPC分类号： H01M10/4257 ,  H01M10/0431 ,  H01M10/4207 ,  H01M10/425 ,  H01M10/48 ,  H01M10/482 ,  H01M2010/4278

摘要： Provided is a secondary battery cell that can certainly prevent detachment of an integrated circuit from the secondary battery cell and attachment of the integrated circuit to another secondary battery cell, a battery pack including such secondary battery cells, and an electric power consumption device including such a battery pack.A secondary battery cell 20 of the present invention includes an integrated circuit (an IC chip) 50 that has stored identification information, and the integrated circuit 50 is driven by power from the secondary battery cell. A battery pack of the present invention includes secondary battery cells each including an integrated circuit (an IC chip) that has stored identification information, and the integrated circuits are driven by power from the secondary battery cells. An electric power consumption device of the present invention contains a battery pack that includes secondary battery cells each including an integrated circuit (an IC chip) that has stored identification information, and the integrated circuits are driven by power from the secondary battery cells.

摘要翻译： 本发明提供二次电池，其可以防止集成电路从二次电池单元的分离和集成电路与另一二次电池单元的连接，包括这种二次电池单元的电池组以及包括这种二次电池的电力消耗装置 电池组。 本发明的二次电池单元20包括具有存储识别信息的集成电路（IC芯片）50，并且集成电路50由来自二次电池单元的电力驱动。 本发明的电池组包括二次电池单元，每个二次电池单元包括具有存储的识别信息的集成电路（IC芯片），并且集成电路由来自二次电池单元的电力驱动。 本发明的电力消耗装置包含电池组，其包括二次电池单元，二次电池单元具有存储了识别信息的集成电路（IC芯片），并且集成电路由来自二次电池单元的电力驱动。

公开(公告)号：US08379843B2

公开(公告)日：2013-02-19

申请号：US12812903

申请日：2009-01-21

申请人： Talzo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

发明人： Talzo Shirai ,  Kyoji Shibutani ,  Shiho Moriai ,  Toru Akishita ,  Tetsu Iwata

IPC分类号： H04L9/00

CPC分类号： H04L9/28 ,  G09C1/00 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/122

摘要： A data conversion algorithm achieving efficient data diffusion is achieved. For example, in a configuration where a various processes are executed on two data segments which are resultants of dividing a rectangular matrix of data containing arranged one-byte data blocks into two parts to perform data conversion, efficient data scrambling with less operation cost is achieved by executing a linear conversion process on one of the data segments, an exclusive OR operation between the two data segments, a shift process on one of the data segments, and a swap process between the two data segments. Moreover, cryptographic processing with a high security level is achieved by including nonlinear conversion or key application operation on the data segments.

摘要翻译： 实现了实现有效数据扩散的数据转换算法。 例如，在将包含排列1字节的数据块的数据的矩形矩阵分割成两部分进行数据转换的两个数据段执行各种处理的结构中，实现了以较少的运算成本的有效数据加扰 通过对数据段之一执行线性转换处理，在两个数据段之间进行异或运算，对数据段之一进行移位处理，以及两个数据段之间的交换处理。 此外，通过在数据段上包括非线性转换或密钥应用操作来实现具有高安全级别的密码处理。

公开(公告)号：US07957527B2

公开(公告)日：2011-06-07

申请号：US11791283

申请日：2005-11-15

申请人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

发明人： Masanobu Katagi ,  Toru Akishita ,  Izuru Kitamura ,  Tsuyoshi Takagi

IPC分类号： H04L9/28 ,  H04L9/30

CPC分类号： G06F7/725 ,  G06F2207/7261

摘要： An apparatus and a method for performing a hyperelliptic curve cryptography process at a high speed in a highly secure manner are provided. A base point D is produced such that the base point D and one or more of precalculated data in addition to the base point used in a scalar multiplication operation based on a window algorithm are degenerate divisors with a weight smaller than genus g of a hyperelliptic curve. An addition operation included in the scalar multiplication operation based on the window algorithm is accomplished by performing an addition operation of adding a degenerate divisor and a non-degenerate divisor, whereby a high-speed operation is achieved without causing degradation in security against key analysis attacks such as SPA.

摘要翻译： 提供了一种以高度安全的方式高速执行超椭圆曲线密码处理的装置和方法。 产生基点D，使得除了基于窗口算法的标量乘法运算中使用的基点之外，基点D和预先计算的数据中的一个或多个是具有小于超椭圆曲线的g的权重的简并因数 。 基于窗口算法的标量乘法运算中包含的加法运算通过执行加法简并因子和非简并因数的加法运算来实现，从而实现高速运算，而不会导致安全性降低密钥分析攻击 如SPA。

公开(公告)号：US07835517B2

公开(公告)日：2010-11-16

申请号：US11653182

申请日：2007-01-12

申请人： Toru Akishita ,  Masanobu Katagi

发明人： Toru Akishita ,  Masanobu Katagi

IPC分类号： H04L9/28

CPC分类号： G06F7/725 ,  G06F7/4824 ,  G06F2207/7261

摘要： An encryption processing apparatus for performing a scalar multiplication of kP+lQ based on two points P and Q on an elliptic curve and scalar values k and l or a scalar multiplication of kD1+lD2 based on divisors D1 and D2 and scalar values k and l may include a scalar value controller configured to generate joint regular form of (k, l), k= and l= , which are set so that all the bits of the scalar values k and l are represented by 0, +1, or −1, and the combination (ki, li) of bits at positions corresponding to the scalar values k and l is set to satisfy (ki, li)=(0, ±1) or (±1, 0); and a computation execution section configured to perform a process for computing a scalar multiplication of kP+lQ or kD1+lD2.

摘要翻译： 一种加密处理装置，用于基于除数D1和D2以及标量值k和l，基于椭圆曲线上的两个点P和Q执行kP + 1Q的标量乘法和标量值k和l或kD1 + 1D2的标量乘法 可以包括被配置为生成（k，l）的联合规则形式的标量值控制器，k = 和l =

公开(公告)号：US20100272253A1

公开(公告)日：2010-10-28

申请号：US12759747

申请日：2010-04-14

申请人： Seiichi MATSUDA ,  Toru Akishita

发明人： Seiichi MATSUDA ,  Toru Akishita

IPC分类号： H04L9/30 ,  H04L9/28

CPC分类号： G06F7/725 ,  G06F2207/7271

摘要： An information processing device includes a scalar multiplication operating unit calculating, based on a point P on an elliptic curve E defined on a predetermined defined field, a point Q=s·P by scalar-multiplying the point P and an operation verifying unit verifying whether an equation (P+Q)+G=P+(Q+G) holds by using the point P on the elliptic curve E, the point Q=s·P calculated by the scalar multiplication operating unit, and an arbitrary point G on the elliptic curve E.

摘要翻译： 信息处理装置包括：标量乘法运算部，基于在规定的定义的场中定义的椭圆曲线E上的点P，通过对点P进行标量乘积的点Q = s·P和运算验证单元来验证是否 通过使用椭圆曲线E上的点P，由标量乘法运算单元计算出的点Q = s·P以及任意点G，可以得到等式（P + Q）+ G = P +（Q + G） 椭圆曲线E.

公开(公告)号：US20100014659A1

公开(公告)日：2010-01-21

申请号：US12439543

申请日：2007-08-29

申请人： Kyoji Shibutani ,  Toru Akishita ,  Shiho Moriai

发明人： Kyoji Shibutani ,  Toru Akishita ,  Shiho Moriai

IPC分类号： H04L9/28

CPC分类号： H04L9/002 ,  H04L9/0625 ,  H04L2209/122 ,  H04L2209/24

摘要： In extended Feistel type common key block cipher processing, a configuration is realized in which an encryption function and a decryption function are commonly used. In a cryptographic processing configuration to which an extended Feistel structure in which the number of data lines d is set to an integer satisfying d≧3 is applied, involution properties, that is, the application of a common function to encryption processing and decryption processing, can be achieved. With a configuration in which round keys are permuted or F-functions are permuted in the decryption processing, processing using a common function can be performed by setting swap functions for the encryption processing and the decryption processing to have the same processing style.

摘要翻译： 在扩展的Feistel型通用密钥块密码处理中，实现了通常使用加密功能和解密功能的配置。 在将数据线数d设定为满足d> = 3的整数的扩展Feistel结构的密码处理配置中，应用归一化属性，即将公共功能应用于加密处理和解密处理 ， 可以实现。 通过在解密处理中将轮密钥置换或F功能配置的配置，可以通过将用于加密处理和解密处理的交换功能设置为具有相同的处理风格来执行使用公共功能的处理。

公开(公告)号：US20080143561A1

公开(公告)日：2008-06-19

申请号：US11948582

申请日：2007-11-30

申请人： Yoshikazu MIYATO ,  Toru Akishita

发明人： Yoshikazu MIYATO ,  Toru Akishita

IPC分类号： H03M7/00

CPC分类号： H03M5/04 ,  H04L9/003 ,  H04L9/0618 ,  H04L2209/12

摘要： An operation processing apparatus adapted to perform a data conversion on input bits has a logic circuit adapted to perform a data conversion on input bits. The logic circuit includes selectors configured in a hierarchical layer structure and controlled by select signals corresponding to the input bits. Constant values input to selectors located in a bottom layer of the hierarchical structure are selected and transferred toward a top layer from one layer to another. A constant value is finally selected and output from the top layer. The data conversion process is controlled by a control unit such that a pre-charge phase and an evaluation phase are performed alternately. In the pre-charge phase, all input values to the selectors are set to be equal. In the evaluation phase, an output bit for given input bits is produced. The select signals are switched in the pre-charge phase.

摘要翻译： 适于对输入比特执行数据转换的操作处理装置具有适于对输入比特执行数据转换的逻辑电路。 逻辑电路包括以分级层结构配置并由对应于输入位的选择信号控制的选择器。 选择输入到位于分层结构底层的选择器的常数值，并将其从顶层转移到另一层。 最后选择一个恒定值并从顶层输出。 数据转换处理由控制单元控制，使得交替执行预充电阶段和评估阶段。 在预充电阶段，选择器的所有输入值都被设置为相等。 在评估阶段，产生给定输入位的输出位。 选择信号在预充电阶段切换。

公开(公告)号：US07177422B2

公开(公告)日：2007-02-13

申请号：US10128805

申请日：2002-04-24

申请人： Toru Akishita

发明人： Toru Akishita

IPC分类号： H04L9/00 ,  G06F7/72

CPC分类号： G06F7/725

摘要： An elliptic curve encryption processing method and an elliptic curve encryption processing apparatus enable high-speed elliptic curve encryption processing computations to be realized. In elliptic curve encryption processing computations, two scalar multiplications, kP and lQ, are not performed separately, but the computation process of kP+lQ is performed simultaneously. In the computation of scalar multiplications, kP and lQ are set on a Montgomery elliptic curve By2=x3+Ax2+x. On the basis of a combination of each bit value of k and l from the high-order bits of the binary representation data of the scalar quantities k and l, a computation relation of the next four points based on the computed four points is selected, and based on the selected relation, a process of computing the next four points is repeatedly performed to eventually compute kP+lQ.

摘要翻译： 椭圆曲线加密处理方法和椭圆曲线加密处理装置能够实现高速椭圆曲线加密处理计算。 在椭圆曲线加密处理计算中，两个标量乘法kP和lQ不是单独执行的，而是同时执行kP + 1Q的计算过程。 在标量乘法的计算中，在蒙哥马利椭圆曲线上设置kP和lQ，由+ 2 + 2 + x2设定。 基于标量k和l的二进制表示数据的高位的k和l的每个比特值的组合，选择基于所计算的四个点的接下来的四个点的计算关系， 并且基于所选择的关系，重复执行计算下一个四点的处理，以最终计算kP + 1Q。