公开(公告)号：US20080143561A1

公开(公告)日：2008-06-19

申请号：US11948582

申请日：2007-11-30

申请人： Yoshikazu MIYATO ,  Toru Akishita

发明人： Yoshikazu MIYATO ,  Toru Akishita

IPC分类号： H03M7/00

CPC分类号： H03M5/04 ,  H04L9/003 ,  H04L9/0618 ,  H04L2209/12

摘要： An operation processing apparatus adapted to perform a data conversion on input bits has a logic circuit adapted to perform a data conversion on input bits. The logic circuit includes selectors configured in a hierarchical layer structure and controlled by select signals corresponding to the input bits. Constant values input to selectors located in a bottom layer of the hierarchical structure are selected and transferred toward a top layer from one layer to another. A constant value is finally selected and output from the top layer. The data conversion process is controlled by a control unit such that a pre-charge phase and an evaluation phase are performed alternately. In the pre-charge phase, all input values to the selectors are set to be equal. In the evaluation phase, an output bit for given input bits is produced. The select signals are switched in the pre-charge phase.

摘要翻译： 适于对输入比特执行数据转换的操作处理装置具有适于对输入比特执行数据转换的逻辑电路。 逻辑电路包括以分级层结构配置并由对应于输入位的选择信号控制的选择器。 选择输入到位于分层结构底层的选择器的常数值，并将其从顶层转移到另一层。 最后选择一个恒定值并从顶层输出。 数据转换处理由控制单元控制，使得交替执行预充电阶段和评估阶段。 在预充电阶段，选择器的所有输入值都被设置为相等。 在评估阶段，产生给定输入位的输出位。 选择信号在预充电阶段切换。

公开(公告)号：US20100281316A1

公开(公告)日：2010-11-04

申请号：US12765476

申请日：2010-04-22

申请人： Yoshikazu MIYATO ,  Masafumi KUSAKAWA

发明人： Yoshikazu MIYATO ,  Masafumi KUSAKAWA

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318536 ,  G11C29/48 ,  G11C2029/3202

摘要： A semiconductor integrated circuit includes a scan chain configured to serve as a connection path used for testing the semiconductor integrated circuit and connect a plurality of flip-flops and an interleave circuit provided at an output portion of the scan chain. The interleave circuit includes a plurality of branches including different numbers of stages of storage elements, a selector configured to select one of the plurality of branches serving as an input/output branch that performs input of data from the scan chain and output of data from the interleave circuit, and a selector controller configured to execute a process of switching among the plurality of branches to select the input/output branch at every predetermined timing.

摘要翻译： 半导体集成电路包括扫描链，其被配置为用作测试半导体集成电路并连接多个触发器的连接路径和设置在扫描链的输出部分处的交错电路。 交错电路包括多个分支，包括不同级别的存储元件，选择器被配置为选择用作输入/输出分支的多个分支之一，该分支执行来自扫描链的数据输入并从 交错电路，以及选择器控制器，被配置为执行在所述多个分支之间切换的处理，以在每个预定定时选择所述输入/输出分支。

公开(公告)号：US20100262830A1

公开(公告)日：2010-10-14

申请号：US12751838

申请日：2010-03-31

申请人： Masafumi KUSAKAWA ,  Yoshikazu MIYATO

发明人： Masafumi KUSAKAWA ,  Yoshikazu MIYATO

IPC分类号： H04L9/32

CPC分类号： G06F21/77

摘要： Provided is an authentication device which includes a register in which a first-bit or a second-bit different from the first-bit is stored, m first determination units for determining whether input information and authentication information match, and for storing the first-bit in the register if a result of the determination is TRUE and for storing the second-bit in the register if FALSE, (N−m) second determination units for determining whether input information and authentication information do not match, and for storing the first-bit in the register if a result of the determination is TRUE and for storing the second-bit in the register if FALSE, and an authentication determination unit for determining that an authentication is established, in case the first-bit is stored in the register by a determination process by every first determination unit and the second-bit is stored in the register by a determination process by every second determination unit.

摘要翻译： 提供了一种认证装置，其包括其中存储与第一比特不同的第一比特或第二比特的寄存器，m个用于确定输入信息和认证信息是否匹配的第一确定单元，以及用于存储第一比特 在所述寄存器中，如果所述确定的结果为真，并且如果用于确定输入信息和认证信息不匹配的FALSE，（N-m）个第二确定单元，并且用于存储所述第一位， 如果确定的结果为真，并且如果FALSE存储在寄存器中的第二位，则存储在寄存器中，以及用于确定认证被建立的认证确定单元，在第一位被存储在寄存器中的情况下 每个第一确定单元和第二位的确定处理通过每个第二确定单元的确定处理被存储在寄存器中。