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公开(公告)号：US20200020698A1
公开(公告)日：2020-01-16
申请号：US16583268
申请日：2019-09-26
Inventor： Pin-Hong Chen , Yi-Wei Chen , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Chi-Mao Hsu
IPC: H01L27/108 , H01L21/768
Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.
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公开(公告)号：US10535664B2
公开(公告)日：2020-01-14
申请号：US16012744
申请日：2018-06-19
Inventor： Po-Chun Chen , Wei-Hsin Liu , Chia-Lung Chang , Yi-Wei Chen , Han-Yung Tsai
IPC: H01L21/336 , H01L27/108 , H01L29/66 , H01L21/02 , H01L21/265 , H01L21/266 , H01L29/78
Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
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公开(公告)号：US20190363093A1
公开(公告)日：2019-11-28
申请号：US16012744
申请日：2018-06-19
Inventor： Po-Chun Chen , Wei-Hsin Liu , Chia-Lung Chang , Yi-Wei Chen , Han-Yung Tsai
IPC: H01L27/108 , H01L29/66 , H01L29/78 , H01L21/265 , H01L21/266 , H01L21/02
Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
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公开(公告)号：US10475900B2
公开(公告)日：2019-11-12
申请号：US15869005
申请日：2018-01-11
Inventor： Kai-Jiun Chang , Tsun-Min Cheng , Chih-Chieh Tsai , Jui-Min Lee , Yi-Wei Chen , Chia-Lung Chang , Wei-Hsin Liu
IPC: H01L29/49 , H01L21/285 , H01L29/66 , H01L27/108 , H01L21/28
Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
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公开(公告)号：US20190319107A1
公开(公告)日：2019-10-17
申请号：US15985730
申请日：2018-05-22
Inventor： Chun-Chieh Chiu , Pin-Hong Chen , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chien Liu , Tzu-Chieh Chen , Chih-Chieh Tsai , Kai-Jiun Chang , Yi-An Huang , Chia-Chen Wu , Tzu-Hao Liu
IPC: H01L29/49 , H01L21/02 , H01L21/3213 , H01L21/28 , H01L29/423 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
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Patent Agency Ranking
公开(公告)号：US10262895B2
公开(公告)日：2019-04-16
申请号：US15859766
申请日：2018-01-02
Inventor： Mei-Ling Chen , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Ching-Hsiang Chang , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L21/02 , H01L21/768 , H01L27/108 , H01L21/8234 , H01L49/02
Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.
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公开(公告)号：US20190027479A1
公开(公告)日：2019-01-24
申请号：US15990837
申请日：2018-05-29
Inventor： Chia-Chen Wu , Yi-Wei Chen , Chi-Mao Hsu , Kai-Jiun Chang , Chih-Chieh Tsai , Pin-Hong Chen , Tsun-Min Cheng , Yi-An Huang
IPC: H01L27/108 , C23C14/06 , C23C14/58 , C23C14/34
Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
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公开(公告)号：US20180361422A1
公开(公告)日：2018-12-20
申请号：US15939305
申请日：2018-03-29
Inventor： Jui-Min Lee , Ching-Hsiang Chang , Cheng-Hsu Huang , Yi-Wei Chen , Wei-Hsin Liu , Shih-Fang Tzou
IPC: B05D1/00 , B05C11/08 , H01L21/02 , H01L21/762
Abstract: A spin-on-dielectric process includes the following steps. A substrate is provided. A flowable material is spread on a surface of the substrate to forma spin-on-dielectric layer on the substrate, wherein the flowable material is heated to a temperature higher than 25° C.
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公开(公告)号：US20180331223A1
公开(公告)日：2018-11-15
申请号：US16028187
申请日：2018-07-05
Applicant: United Microelectronics Corp.
Inventor： Man-Ling Lu , Yu-Hsiang Hung , Chung-Fu Chang , Yen-Liang Wu , Wen-Jiun Shen , Chia-Jong Liu , Ssu-I Fu , Yi-Wei Chen
IPC: H01L29/78 , H01L29/66 , H01L21/308
CPC classification number: H01L29/7848 , H01L21/3086 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/78
Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
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公开(公告)号：US20180212034A1
公开(公告)日：2018-07-26
申请号：US15869005
申请日：2018-01-11
Inventor： Kai-Jiun Chang , Tsun-Min Cheng , Chih-Chieh Tsai , Jui-Min Lee , Yi-Wei Chen , Chia-Lung Chang , Wei-Hsin Liu
IPC: H01L29/49 , H01L29/66 , H01L21/28 , H01L21/285 , H01L27/108
Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.
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