公开(公告)号：US10169521B2

公开(公告)日：2019-01-01

申请号：US15479271

申请日：2017-04-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Chien-Ting Ho ,  Li-Wei Feng ,  Emily SH Huang

IPC: G06F17/00 ,  G06F17/50 ,  H01L27/02 ,  H01L27/108

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

公开(公告)号：US10103150B1

公开(公告)日：2018-10-16

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US20180294266A1

公开(公告)日：2018-10-11

申请号：US15585180

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng

IPC: H01L27/108 ,  H01L23/528

Abstract: The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.

公开(公告)号：US20180190664A1

公开(公告)日：2018-07-05

申请号：US15856022

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chien-Cheng Tsai ,  Feng-Ming Huang ,  Ying-Chiao Wang ,  Chien-Ting Ho ,  Li-Wei Feng ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.

公开(公告)号：US09929162B1

公开(公告)日：2018-03-27

申请号：US15456564

申请日：2017-03-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Yu-Chieh Lin ,  Chien-Ting Ho

IPC: H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.

公开(公告)号：US09679901B1

公开(公告)日：2017-06-13

申请号：US15296955

申请日：2016-10-18

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ying-Chiao Wang ,  Chien-Ting Ho ,  Le-Tien Jung ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Harn-Jiunn Wang

IPC: H01L21/762 ,  H01L27/108 ,  H01L29/06 ,  H01L21/461

CPC classification number: H01L27/10894 ,  H01L21/461 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.

公开(公告)号：US11049863B2

公开(公告)日：2021-06-29

申请号：US15889182

申请日：2018-02-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Ting Ho ,  Ying-Chiao Wang ,  Yu-Ching Chen ,  Hui-Ling Chuang ,  Kuei-Hsuan Yu

IPC: H01L27/108

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

公开(公告)号：US20200350317A1

公开(公告)日：2020-11-05

申请号：US16931397

申请日：2020-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10756090B2

公开(公告)日：2020-08-25

申请号：US15922899

申请日：2018-03-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L21/8242 ,  H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/02

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US10665594B2

公开(公告)日：2020-05-26

申请号：US16036908

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Shih-Fang Tzou

IPC: H01L29/49 ,  H01L27/108 ,  H01L23/535 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.