摘要:
A decoding unit for decoding a modulated signal includes a summing unit having i) a first input, ii) a second input, and iii) an output. The summing unit is configured to i) receive the modulated signal at the first input, ii) receive a feedback signal at the second input, and iii) output a first waveform based on the modulated signal and the feedback signal. A demodulation unit has a first demodulation pathway and a second demodulation pathway. The demodulation unit is configured to i) select between the first demodulation pathway and the second demodulation pathway, ii) receive and demodulate the modulated signal with the first demodulation pathway, and iii) receive and demodulate the first waveform with the second demodulation pathway. The remodulation unit is configured to selectively i) output a first complex waveform based on the modulated signal, and ii) output a subsymbol waveform of the first waveform.
摘要:
A network device includes a first demodulation path to recover a header portion of a data packet. A second demodulation path recovers a payload portion of the data packet. The second demodulation path includes a down sampler to down sample a payload portion of the data packet. An equalizer equalizes an output of the down sampler. A correlator receives an output of the equalizer. A demodulation controller selects the output of the equalizer or an output of the correlator based on the header portion.
摘要:
A system comprises a circuit that stores a first value and M parallel signal lines that communicate with the circuit, where M is an integer greater than three. A difference controller that receives the first value via the M parallel signal lines, that compares the first value to a first reference value, and that generates control signals based on a difference between the first value and the first reference value. An accumulator circuit that communicates with N signal lines, that stores a second reference value and that performs one of increment and decrement function to adjust the second reference value based on the control signals, where N is less than or equal to three.
摘要:
Techniques for and apparatus capable of implementing packet detection and signal recognition in wireless communications systems are disclosed. In particular, the disclosed techniques and apparatus incorporate at least one of relative energy detection operable on assessment of a relative energy threshold for an inbound signal borne across an RF channel, carrier sense operable upon on assessment of at least one of a peak-to-sidelobe ratio and peak-to-peak distance defined by the inbound signal, and comparison operable upon demodulated data corresponding to the inbound signal as compared to predetermined preamble data. Clear channel assessment is performed based on determinations undertaken by one or more of the aforementioned relative energy detection, carrier sense and comparison operations.
摘要:
A system includes a signal processing module and a control module. The signal processing module receives a first clear channel assessment (CCA) signal for a first sub-channel of a communication channel, increases a pulse width of the first CCA signal by a predetermined period of time, and generates a second CCA signal. The control module receives the second CCA signal and a third CCA signal for a second sub-channel of the communication channel. The control module transmits data via one of the second sub-channel and the communication channel based on the second and third CCA signals.
摘要:
Method and apparatus for communicating numeric data between first and second circuits incorporating a controller communicatively coupled to the first circuit to receive the numeric data, and an accumulator communicatively coupled to the second circuit and the controller, the accumulator comprising accumulator logic managing reference data, the controller being responsive to the numeric data selectively causing the accumulator logic to increment or decrement the reference data to match the numeric data. The accumulator will notify the second circuit of the so-updated reference data. In one embodiment, three signal lines (UP, DN, CLK) are used by the controller to direct the accumulator to increment, decrement, reset or hold the reference data. In another embodiment, only two signal lines are used at the expense of reset complexity.
摘要:
Method and apparatus for high speed wireless transmission involving selective PSK coding techniques are disclosed. In particular, to enhance effective throughput while maintaining a channel footprint backwards compatible with existing IEEE 802.11 and 802.11b (1999) standards, the payload of outbound data packets are selectively modulated using DQPSK techniques at the CCK symbol chipping rate. This results in a 22 Mbps effective throughput, a 2× improvement over the 802.11b standard. A complementary receiver includes a DQPSK demodulation pathway suitable for decoding inbound data packets at the 11 MHz CCK chipping rate but bypassing the conventional CCK encoder, resulting in a 22 Mbps data stream. Backwards compatibility with legacy 802.11 and 802.11b devices is partially accommodated using a data packet format similar to the conventional PLCP frame format but for the data transmission rate and use of heretofore reserved bits, causing legacy devices to ignore such packets.
摘要:
Method and apparatus for constraining tap coefficients in an adaptive Finite Impulse Response filter includes structure and steps whereby a coefficient supply circuit provides at least two even tap coefficients and at least two odd tap coefficients to the adaptive Finite Impulse Response filter. Constraint circuitry then selectively constrains changes in the values of at least one of (i) the two even tap coefficients and (ii) the two odd tap coefficients. Preferably, the Finite Impulse Response filter has taps C0, C1, C2, C3, C4, C5, and C6. A coefficient supplier is coupled to provide coefficients to said taps, and an adaptive circuit changes the coefficients supplied by said coefficient supplier in accordance with changes in an output of the Finite Impulse Response filter. The adaptive circuit includes circuitry to constrain allowable change in both the even tap coefficients C0, C2, C4, C6 and in the odd tap coefficients C1, C3, C5.