Fingerprint sensor and interface
    41.
    发明授权
    Fingerprint sensor and interface 有权
    指纹传感器和接口

    公开(公告)号:US07978884B1

    公开(公告)日:2011-07-12

    申请号:US11832763

    申请日:2007-08-02

    CPC classification number: G06K9/00006

    Abstract: A fingerprint sensor interface that connects to a standard camera interface and minimizes input and output signals to reduce sensor die area and cost. The sensor can connect to a standard camera interface of a cellular telephone baseband processor or other device intended to receive signals from a camera. Input and output pad are arranged on a single edge of the die. Circuitry between the pads and the sensor active array creates clearance from the array to the bond wires connected to the pads.

    Abstract translation: 指纹传感器接口连接到标准摄像头接口,并最大限度地减少输入和输出信号,从而降低传感器裸片面积和成本。 传感器可以连接到蜂窝电话基带处理器或其他旨在从相机接收信号的设备的标准摄像机接口。 输入和输出焊盘布置在芯片的单个边缘上。 焊盘和传感器有源阵列之间的电路产生从阵列到连接到焊盘的接合线的间隙。

    Gesturing architecture using proximity sensing
    42.
    发明授权
    Gesturing architecture using proximity sensing 有权
    使用接近感测的手势架构

    公开(公告)号:US09298333B2

    公开(公告)日:2016-03-29

    申请号:US13334477

    申请日:2011-12-22

    Applicant: Kenneth W. Gay

    Inventor: Kenneth W. Gay

    CPC classification number: G06F3/046 G01S13/04 G06F3/044

    Abstract: Proximity based system and method for detecting user gestures. Each of a plurality of proximity sensing circuits may collect digital data. Each proximity sensing circuit may include an antenna configured to transmit and receive electromagnetic signals and a shield driver configured to shield signals transmitted by the antenna in one or more directions. The digital data may be collected based on electromagnetic signals received from another proximity sensing circuit via the antenna. The received electromagnetic signals may be modified by one or more user proximity gestures. The digital data from each of the plurality of proximity sensing circuits may be received by a coordinating circuit. The coordinating circuit may produce coordinated digital data from the digital data received from each of the plurality of proximity sensing circuits. The coordinated digital data may be configured for use in determining that a user performed the one or more user proximity gestures.

    Abstract translation: 用于检测用户手势的接近系统和方法。 多个接近感测电路中的每一个可以收集数字数据。 每个接近感测电路可以包括被配置为发送和接收电磁信号的天线以及被配置为屏蔽由一个或多个方向发射的天线的信号的屏蔽驱动器。 可以基于经由天线从另一接近感测电路接收的电磁信号来收集数字数据。 所接收的电磁信号可以被一个或多个用户接近手势修改。 来自多个接近感测电路中的每一个的数字数据可以由协调电路接收。 协调电路可以从从多个接近感测电路中的每一个接收的数字数据产生协调的数字数据。 协调的数字数据可以被配置为用于确定用户执行一个或多个用户接近手势。

    Overcoming limited common-mode range for USB systems
    44.
    发明授权
    Overcoming limited common-mode range for USB systems 有权
    克服USB系统的有限共模范围

    公开(公告)号:US08990592B2

    公开(公告)日:2015-03-24

    申请号:US13357987

    申请日:2012-01-25

    CPC classification number: G06F13/426 G06F13/4072

    Abstract: An intelligent level shifter may be added to adjust the voltage level on the data lines (D+ and D−) used for communications in USB systems, to address the issue of missing negative common-mode range as defined by the USB specification. The level shifter may be part of a port power controller that allows adaptive shifting of the signal level in accordance with the current levels drawn on the supply line by a device, for example during charging. The port power controller may be operated in systems enabled for battery charging, and may combine overcurrent sensing (current meter for VBus) and the routing of the D+ and D− lines (used for the battery charging protocol) into a single package. By varying the voltage levels on the D+ and D− data lines according to the drawn current levels, the performance of USB Hosts ports and USB Hub ports may be greatly increased.

    Abstract translation: 可以添加智能电平转换器来调整用于USB系统通信的数据线(D +和D-)上的电压电平,以解决由USB规范定义的丢失负共模范围的问题。 电平移位器可以是端口功率控制器的一部分,其允许根据设备在电源线上绘制的电流水平(例如在充电期间)自适应地移动信号电平。 端口功率控制器可以在能够进行电池充电的系统中运行,并且可以将过电流检测(VBus的电流表)和用于电池充电协议的D +和D-线的路由组合成单个封装。 通过根据绘制的电流电平改变D +和D-数据线上的电压电平,可以大大提高USB主机端口和USB集线器端口的性能。

    Systems and methods for locking an oscillator to an incoming data signal
    45.
    发明授权
    Systems and methods for locking an oscillator to an incoming data signal 有权
    将振荡器锁定到输入数据信号的系统和方法

    公开(公告)号:US08971423B1

    公开(公告)日:2015-03-03

    申请号:US12721432

    申请日:2010-03-10

    CPC classification number: H03L7/0807 H03L7/0895 H03L7/093 H03L7/113

    Abstract: In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.

    Abstract translation: 在一个示例中,系统包括适于提供振荡器信号的振荡器,适于分频振荡器信号以提供分频振荡器信号的分频器,以及相位频率检测器,其适于响应于 参考时钟信号和分频振荡器信号。 该系统还包括适于响应于相位频率检测信号提供第一输出信号的电荷泵,相位检测器适于响应输入数据信号和振荡器信号提供第二输出信号,以及一个或多个开关,适于 在频率获取模式期间传递第一输出信号,并在锁相模式期间传递第二输出信号。 该系统还包括适用于过滤所传送的第一或第二输出信号的有源滤波器。 振荡器适于响应于滤波的第一或第二输出信号来调整振荡器信号的频率。

    System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios
    46.
    发明授权
    System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios 有权
    通过选择性地划分具有多个比率的参考时钟信号来产生多个通信端口的时钟信号的系统和方法

    公开(公告)号:US08775856B1

    公开(公告)日:2014-07-08

    申请号:US12721447

    申请日:2010-03-10

    CPC classification number: G06F1/06

    Abstract: Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

    Abstract translation: 提供各种技术以使用单个参考时钟信号发生器产生多个参考时钟信号。 在一个示例中,时钟信号产生系统包括适于提供参考时钟信号的参考时钟信号发生器。 该系统还包括多个分频器,其适于使用不同的比率划分参考时钟信号以提供多个通信端口时钟信号。 该系统还包括多个不同的通信端口,其适于接收通信端口时钟信号并且适于根据使用通信端口时钟信号的不同通信协议进行操作。

    Systems and methods for high speed data recovery with free running sampling clock
    47.
    发明授权
    Systems and methods for high speed data recovery with free running sampling clock 有权
    采用自由运行采样时钟的高速数据恢复系统和方法

    公开(公告)号:US08666006B1

    公开(公告)日:2014-03-04

    申请号:US13035213

    申请日:2011-02-25

    CPC classification number: H04L7/0337

    Abstract: Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.

    Abstract translation: 公开了用于改进数据收发器或接收机中的接收数据流的高速数据的数字前馈数据恢复的系统和方法,其中接收器时钟与用于发送所接收的数据流的发射机时钟异步。 在一个示例中,使用N个均匀间隔的多相时钟对接收到的数据流进行过采样。 过采样数据被打包成数据块。 跟踪数据块中相对于多相时钟的过采样数据的数据转移边缘。 跟踪的数据转换边缘用于确定判定窗口的长度,并且进一步将过采样数据划分成被假定为相同接收数据符号的样本的位组。 在决策窗口执行位映射以恢复接收到的数据符号。 通过跟踪数据转换边缘的移动,该技术增强了数据恢复能力。

    Method for synchronization in networks
    48.
    发明授权
    Method for synchronization in networks 有权
    网络同步方法

    公开(公告)号:US08601165B2

    公开(公告)日:2013-12-03

    申请号:US12732654

    申请日:2010-03-26

    CPC classification number: H04L12/1485 H04J3/0664 H04J3/0673

    Abstract: The invention relates to a method for synchronization in networks, whereby the local time (tloc) which is valid at the particular node, is updated at different nodes. For that purpose, timing messages are regularly transmitted by a freely selectable superior node (N1; N3; N6) and only by a superior node to an inferior node (N2, N3; N4-N6; N7), which receives the timing messages (M1-M8) and analyzes said messages for updating the local time (tloc) thereof. A minimum propagation time (dmin) is determined for a timing message (M1-M8) between an inferior node (N1; N3; N6) and a superior node (N2, N3; N4-N6; N7). When the inferior node (N2, N3; N4-N6; N7) receives a timing message (M1-M8), said inferior node extracts the local time of the superior node (N1; N3), which is contained in said timing message (M1-M8) and adds the minimum propagation time (dmin) thereto, in order to generate a reference time (tcomp,1-tcomp,8). Said reference time (tcomp,1-tcomp,8) is then compared with the proper local time (tloc). If the reference time is retarded in relation to the proper local time (tloc), said proper local time (tloc) is not updated. If said reference time is advanced in relation to the proper local time (tloc).

    Abstract translation: 本发明涉及一种在网络中进行同步的方法,由此在特定节点处有效的本地时间(tloc)在不同的节点被更新。 为此,定时消息由可自由选择的上级节点(N1; N3; N6)定期发送,并且仅由上级节点发送到接收定时消息的下级节点(N2,N3; N4-N6; N7) M1-M8)并且分析用于更新其本地时间(tloc)的所述消息。 对于下级节点(N1; N3; N6)和上级节点(N2,N3; N4-N6; N7)之间的定时消息(M1-M8)确定最小传播时间(dmin)。 当下级节点(N2,N3; N4-N6; N7)接收到定时消息(M1-M8)时,所述下级节点提取包含在所述定时消息中的上级节点(N1; N3)的本地时间 M1-M8),并且向其添加最小传播时间(dmin),以产生参考时间(tcomp,1-tcomp,8)。 然后将所述参考时间(tcomp,1-tcomp,8)与适当的本地时间(tloc)进行比较。 如果参考时间相对于正确的本地时间(tloc)延迟,则所述适当的本地时间(tloc)不被更新。 如果所述参考时间相对于适当的当地时间(tloc)提前。

    Low-power class D amplifier using multistate analog feedback loops
    49.
    发明授权
    Low-power class D amplifier using multistate analog feedback loops 有权
    低功耗D类放大器,采用多态模拟反馈回路

    公开(公告)号:US08553909B2

    公开(公告)日:2013-10-08

    申请号:US13097690

    申请日:2011-04-29

    CPC classification number: H03F3/217

    Abstract: An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.

    Abstract translation: 音频放大器系统可以包括具有模拟D类放大器的音频CODEC /输出(AOP)路径,并且使用自然采样脉宽调制(PWM)将模拟输入转换成一系列轨至轨脉冲。 音频信号可以以PWM脉冲序列的平均值编码,并且可以通过模拟低通滤波从PWM信号中恢复。 D类放大器可以设计有负反馈回路/网络,以将输出信号与输入信号进行比较,并抑制D类切换级引入的非理想性。 此外,可以根据单独的信号传递函数和单独的噪声传递函数来设计AOP的操作,并且可以以低功率执行二阶噪声整形,其中包括在反馈环路中的优化滤波器以实现最佳降噪 在低功率。 放大器反馈网络的操作可能类似于连续时间低通量Δ-Σ调制器的操作,但是使用包围D类功率放大器的PWM环路。

    Efficient use of flash memory in flash drives
    50.
    发明授权
    Efficient use of flash memory in flash drives 有权
    在闪存驱动器中高效地使用闪存

    公开(公告)号:US08489803B2

    公开(公告)日:2013-07-16

    申请号:US12637322

    申请日:2009-12-14

    CPC classification number: G06F13/385 G06F2213/3812 G06F2213/3854

    Abstract: A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command.

    Abstract translation: 具有非易失性固态存储器的数据存储设备通过允许来自主机设备的多个未决命令来允许有效的访问。 数据存储装置中的控制器存储关于来自主机设备的每个命令的信息,并且基于非易失性存储器的部分和命令的访问类型确定当前能够执行哪个存储命令(如果有的话) 。 数据存储装置通过允许访问存储器的空闲部分继续进行访问,并且当数据存储装置通过信令主机装置提供减少的访问延迟,提高读/写吞吐量并避免数据存储装置中附加存储器的成本 能够接受由于先前的命令而被写入已经活动的非易失性存储器的部分的数据。

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