Abstract:
A fingerprint sensor interface that connects to a standard camera interface and minimizes input and output signals to reduce sensor die area and cost. The sensor can connect to a standard camera interface of a cellular telephone baseband processor or other device intended to receive signals from a camera. Input and output pad are arranged on a single edge of the die. Circuitry between the pads and the sensor active array creates clearance from the array to the bond wires connected to the pads.
Abstract:
Proximity based system and method for detecting user gestures. Each of a plurality of proximity sensing circuits may collect digital data. Each proximity sensing circuit may include an antenna configured to transmit and receive electromagnetic signals and a shield driver configured to shield signals transmitted by the antenna in one or more directions. The digital data may be collected based on electromagnetic signals received from another proximity sensing circuit via the antenna. The received electromagnetic signals may be modified by one or more user proximity gestures. The digital data from each of the plurality of proximity sensing circuits may be received by a coordinating circuit. The coordinating circuit may produce coordinated digital data from the digital data received from each of the plurality of proximity sensing circuits. The coordinated digital data may be configured for use in determining that a user performed the one or more user proximity gestures.
Abstract:
A wireless adapter enables communication between a content source and a content player for rendering of content at the content source by the content player, and a remote controller allows for control of the content delivery, and one or more features of the content source, player, or both.
Abstract:
An intelligent level shifter may be added to adjust the voltage level on the data lines (D+ and D−) used for communications in USB systems, to address the issue of missing negative common-mode range as defined by the USB specification. The level shifter may be part of a port power controller that allows adaptive shifting of the signal level in accordance with the current levels drawn on the supply line by a device, for example during charging. The port power controller may be operated in systems enabled for battery charging, and may combine overcurrent sensing (current meter for VBus) and the routing of the D+ and D− lines (used for the battery charging protocol) into a single package. By varying the voltage levels on the D+ and D− data lines according to the drawn current levels, the performance of USB Hosts ports and USB Hub ports may be greatly increased.
Abstract:
In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.
Abstract:
Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.
Abstract:
Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is asynchronous to the transmitter clock used to transmit the received data stream. In one example, the received data stream is oversampled using N evenly-spaced multi-phase clocks. The oversampled data are packed into a data block. Data transition edges of the oversampled data in the data blocks with respect to multi-phase clocks are tracked. The tracked data transition edges are used to determine the length of a decision window and to further divide the oversampled data into groups of bits that are hypothesized to be samples of the same received data symbol. Bit mapping is performed on the decision window to recover the received data symbol. By tracking the movement of data transition edges, the technique enhances data recovery capability.
Abstract:
The invention relates to a method for synchronization in networks, whereby the local time (tloc) which is valid at the particular node, is updated at different nodes. For that purpose, timing messages are regularly transmitted by a freely selectable superior node (N1; N3; N6) and only by a superior node to an inferior node (N2, N3; N4-N6; N7), which receives the timing messages (M1-M8) and analyzes said messages for updating the local time (tloc) thereof. A minimum propagation time (dmin) is determined for a timing message (M1-M8) between an inferior node (N1; N3; N6) and a superior node (N2, N3; N4-N6; N7). When the inferior node (N2, N3; N4-N6; N7) receives a timing message (M1-M8), said inferior node extracts the local time of the superior node (N1; N3), which is contained in said timing message (M1-M8) and adds the minimum propagation time (dmin) thereto, in order to generate a reference time (tcomp,1-tcomp,8). Said reference time (tcomp,1-tcomp,8) is then compared with the proper local time (tloc). If the reference time is retarded in relation to the proper local time (tloc), said proper local time (tloc) is not updated. If said reference time is advanced in relation to the proper local time (tloc).
Abstract:
An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.
Abstract:
A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command.