INCREASING THE SNR OF SUCCESSIVE APPROXIMATION TYPE ADCS WITHOUT COMPROMISING THROUGHPUT PERFORMANCE SUBSTANTIALLY
    41.
    发明申请
    INCREASING THE SNR OF SUCCESSIVE APPROXIMATION TYPE ADCS WITHOUT COMPROMISING THROUGHPUT PERFORMANCE SUBSTANTIALLY 有权
    提高连续逼近型ADCS的信噪比,而不会影响实质性能

    公开(公告)号:US20050057387A1

    公开(公告)日:2005-03-17

    申请号:US10663729

    申请日:2003-09-17

    CPC classification number: H03M1/06 H03M1/0656 H03M1/208

    Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.

    Abstract translation: 通过从相同的模拟采样产生多个N位代码并对N位代码进行平均,将模拟信号转换为N位数字码,具有高SNR(信噪比)。 然而,整个N位代码仅被确定一次,并且仅产生P位(P小于N)个代码。 可以对P位代码进行平均,并且基于平均值校正N位代码以产生精确的N位数字代码。 由于P可以远小于N,所以可以在几次迭代中实现校正,从而使得能够以高吞吐量性能实现ADC。 由于校正,也可以获得高SNR。

    Stepwise adjusted digital to analog converter having self correction
    42.
    发明授权
    Stepwise adjusted digital to analog converter having self correction 失效
    逐步调整的数模转换器具有自校正功能

    公开(公告)号:US4940978A

    公开(公告)日:1990-07-10

    申请号:US197737

    申请日:1988-05-23

    CPC classification number: H03M1/0656 H03M1/667

    Abstract: A highly accurate, inexpensive digital to analog converter requiring minimal accuracy in component values. A digital word is received serially, the least significant bit first. A voltage is stored on a capacitor at each bit, the value of the voltage being halfway between a reference voltage and the previously stored voltage, the reference voltage value depending on whether the bit is a logic "1" or "0". In each case, the halfway point of the voltage difference is determined by coupling to the midpoint of a pair of resistive components having essentially the same value. The value of the stored voltage represents the analog value of the digital word. The process is preferably repeated for the same word and the two resulting final voltages is averaged to eliminate any effect of a slight difference in component values in a pair.

    Abstract translation: 高精度,便宜的数模转换器,要求组件值的精度要求最低。 数字字串行接收,最低有效位。 电压在每个位存储在电容器上,电压值在参考电压和先前存储的电压之间,基准电压值取决于该位是逻辑“1”还是“0”。 在每种情况下,电压差的中点通过耦合到具有基本相同值的一对电阻分量的中点来确定。 存储电压的值表示数字字的模拟值。 对于相同的字,优选地重复该过程,并且平均两个得到的最终电压以消除一对中元件值的轻微差异的任何影响。

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