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公开(公告)号：US20140070968A1
公开(公告)日：2014-03-13
申请号：US13607132
申请日：2012-09-07
Applicant: Seetharaman Janakiraman , Minkle Eldho Paul
Inventor： Seetharaman Janakiraman , Minkle Eldho Paul
CPC classification number: H03M1/0697 , H03M1/468
Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.
Abstract translation: SAR ADC的一组中间位分别从第一组代表性电容器和第二组代表性电容器转换成第一中间模拟值和第二中间模拟值。 第一组和第二组中的电容器被选择为不相同。 SAR ADC输出代码由第一中间模拟值和第二中间模拟值产生。 可以通过产生多于一个N位数字代码来增强N位SAR ADC的分辨率，从而相应地运行具有多于传输函数的N位SARADC。 选择每个传递函数使得它们被LSB值的一部分偏移。 然后添加多于一个N位数字码，以形成P位数字码，使得由于相加而使P大于N。
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公开(公告)号：US08258991B2
公开(公告)日：2012-09-04
申请号：US12857976
申请日：2010-08-17
Applicant: Seetharaman Janakiraman
Inventor： Seetharaman Janakiraman
IPC: H03M1/38
CPC classification number: H03K5/249 , H03K5/2481 , H03M1/129 , H03M1/46
Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved.
Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）通常使用一个或多个比较器将模拟信号转换为数字信号。 然而，这些比较器可以消耗大量功率，因此希望具有消耗更少功率的比较器配置。 这里提供了一个多带宽比较器，可以在不同的粗分辨率和精细分辨率之间进行切换。 通过使用该单个多带宽比较器，可以实现较少的功率消耗与少量的面积。
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3.发明申请CORRECTING FOR ERRORS THAT CAUSE GENERATED DIGITAL CODES TO DEVIATE FROM EXPECTED VALUES IN AN ADC 有权纠正错误，导致产生的数字代码来自ADC中的预期值公开(公告)号：US20080186214A1
公开(公告)日：2008-08-07
申请号：US11755011
申请日：2007-05-30
Applicant: Seetharaman Janakiraman
Inventor： Seetharaman Janakiraman
IPC: H03M1/14
CPC classification number: H03M1/0809 , H03M1/38
Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.
Abstract translation: 导致产生的数字代码偏离预期值的模数转换器中的错误被更正。 模拟信号的样本被存储在存储元件中。 然后产生误差信号，其中误差信号表示模拟输入的样本的强度的预期数字代码与将被产生而不进行校正的值的偏差。 然后将误差信号添加到存储的样品。 在SAR ADC的上下文中实现的实施例中，基于部分数字码（样本的部分转换的结果）和误差系数来生成表示积分非线性误差的数字值。 数字值由辅助DAC转换为模拟形式，并添加到存储的输入采样。
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4.发明授权Increasing the SNR of successive approximation type ADCs without compromising throughput performance substantially 有权增加逐次逼近型ADC的SNR，而不会大大降低吞吐量性能公开(公告)号：US06894627B2
公开(公告)日：2005-05-17
申请号：US10663729
申请日：2003-09-17
Applicant: Seetharaman Janakiraman , Kiran Manohar Godbole , Surendranath Nagesh
Inventor： Seetharaman Janakiraman , Kiran Manohar Godbole , Surendranath Nagesh
CPC classification number: H03M1/06 , H03M1/0656 , H03M1/208
Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.
Abstract translation: 通过从相同的模拟采样产生多个N位代码并对N位代码进行平均，将模拟信号转换为N位数字码，具有高SNR（信噪比）。 然而，整个N位代码仅被确定一次，并且仅产生P位（P小于N）个代码。 可以对P位代码进行平均，并且基于平均值校正N位代码以产生精确的N位数字代码。 由于P可以远小于N，所以可以在几次迭代中实现校正，从而使得能够以高吞吐量性能实现ADC。 由于校正，也可以获得高SNR。
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Patent Agency Ranking
5.发明授权SAR ADC providing digital codes with high accuracy and high throughput performance 有权SAR ADC提供高精度和高吞吐量性能的数字代码公开(公告)号：US06958722B1
公开(公告)日：2005-10-25
申请号：US10709996
申请日：2004-06-11
Applicant: Seetharaman Janakiraman , Vikram Varma , Yujendra Mitikiri
Inventor： Seetharaman Janakiraman , Vikram Varma , Yujendra Mitikiri
Abstract: An aspect of the invention improves accuracy of digital codes generated at the output of a SAR ADC by using multiple reference voltages. A first reference voltage is used to generate an equivalent voltage corresponding to previous resolved bits and a second reference voltage is used to generate equivalent voltage corresponding to the bits being presently resolved. Another aspect of the present invention provides an ADC with high SNR as well as high throughput performance. Such a feature may be achieved by resolving some of the MSBs of the digital code using a high speed and low SNR DAC and remaining bits of the digital code using a high SNR DAC.
Abstract translation: 本发明的一个方面通过使用多个参考电压来提高在SAR ADC的输出处产生的数字代码的精度。 使用第一参考电压来产生对应于先前分辨的位的等效电压，并且使用第二参考电压来产生对应于当前解析的位的等效电压。 本发明的另一方面提供了一种具有高信噪比和高吞吐量性能的ADC。 这样的特征可以通过使用高SNR和低SNR DAC解析数字码的一些MSB而使用高SNR DAC来解析数字码的剩余位来实现。
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公开(公告)号：US08766839B2
公开(公告)日：2014-07-01
申请号：US13607132
申请日：2012-09-07
Applicant: Seetharaman Janakiraman , Minkle Eldho Paul
Inventor： Seetharaman Janakiraman , Minkle Eldho Paul
IPC: H03M1/66
CPC classification number: H03M1/0697 , H03M1/468
Abstract: An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.
Abstract translation: SAR ADC的一组中间位分别从第一组代表性电容器和第二组代表性电容器转换成第一中间模拟值和第二中间模拟值。 第一组和第二组中的电容器被选择为不相同。 SAR ADC输出代码由第一中间模拟值和第二中间模拟值产生。 可以通过产生多于一个N位数字代码来增强N位SAR ADC的分辨率，从而相应地运行具有多于传输函数的N位SARADC。 选择每个传递函数使得它们被LSB值的一部分偏移。 然后添加多于一个N位数字码，以形成P位数字码，使得由于相加而使P大于N。
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公开(公告)号：US20110304490A1
公开(公告)日：2011-12-15
申请号：US12857976
申请日：2010-08-17
Applicant: Seetharaman Janakiraman
Inventor： Seetharaman Janakiraman
CPC classification number: H03K5/249 , H03K5/2481 , H03M1/129 , H03M1/46
Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved.
Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）通常使用一个或多个比较器将模拟信号转换为数字信号。 然而，这些比较器可以消耗大量功率，因此希望具有消耗更少功率的比较器配置。 这里提供了一个多带宽比较器，可以在不同的粗分辨率和精细分辨率之间进行切换。 通过使用该单个多带宽比较器，可以实现较少的功率消耗与少量的面积。
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8.发明授权Correcting for errors that cause generated digital codes to deviate from expected values in an ADC 有权校正导致生成的数字代码偏离ADC中预期值的错误公开(公告)号：US07501965B2
公开(公告)日：2009-03-10
申请号：US11755011
申请日：2007-05-30
Applicant: Seetharaman Janakiraman
Inventor： Seetharaman Janakiraman
IPC: H03M1/06
CPC classification number: H03M1/0809 , H03M1/38
Abstract: Errors in an analog to digital converter that cause generated digital codes to deviate from expected values are corrected. A sample of an analog signal is stored in a storage element. An error signal is then generated, with the error signal representing a deviation of an expected digital code for the strength of a sample of an analog input from a value that would be generated without correction. The error signal is then added to the stored sample. In an embodiment implemented in the context of a SAR ADC, a digital value representing an integral non-linearity error is generated based on a partial digital code (result of a partial conversion of the sample) and an error coefficient. The digital value is converted to analog form by an auxiliary DAC, and added to the stored input sample.
Abstract translation: 导致产生的数字代码偏离预期值的模数转换器中的错误被更正。 模拟信号的样本被存储在存储元件中。 然后产生误差信号，其中误差信号表示模拟输入的样本的强度的预期数字代码与将被产生而不进行校正的值的偏差。 然后将误差信号添加到存储的样品。 在SAR ADC的上下文中实现的实施例中，基于部分数字码（样本的部分转换的结果）和误差系数来生成表示积分非线性误差的数字值。 数字值由辅助DAC转换为模拟形式，并添加到存储的输入采样。
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9.发明申请INCREASING THE SNR OF SUCCESSIVE APPROXIMATION TYPE ADCS WITHOUT COMPROMISING THROUGHPUT PERFORMANCE SUBSTANTIALLY 有权提高连续逼近型ADCS的信噪比，而不会影响实质性能公开(公告)号：US20050057387A1
公开(公告)日：2005-03-17
申请号：US10663729
申请日：2003-09-17
Applicant: Seetharaman Janakiraman , Kiran Godbole , Surendranath Nagesh
Inventor： Seetharaman Janakiraman , Kiran Godbole , Surendranath Nagesh
CPC classification number: H03M1/06 , H03M1/0656 , H03M1/208
Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.
Abstract translation: 通过从相同的模拟采样产生多个N位代码并对N位代码进行平均，将模拟信号转换为N位数字码，具有高SNR（信噪比）。 然而，整个N位代码仅被确定一次，并且仅产生P位（P小于N）个代码。 可以对P位代码进行平均，并且基于平均值校正N位代码以产生精确的N位数字代码。 由于P可以远小于N，所以可以在几次迭代中实现校正，从而使得能够以高吞吐量性能实现ADC。 由于校正，也可以获得高SNR。
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