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公开(公告)号：US08749419B2
公开(公告)日：2014-06-10
申请号：US13389663
申请日：2010-08-09
Applicant: Oystein Moldsvor
Inventor： Oystein Moldsvor
IPC: H03M1/12
CPC classification number: H03M1/0845 , H03M1/0643 , H03M1/0656 , H03M1/12 , H03M1/1255
Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.
Abstract translation: 模数转换器包括输入信号连接器，输出信号端口，两个或多个子ADC，以及数字信号处理块。 每个子ADC的结果由数字信号处理块用于以更高的性能输出数据。
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公开(公告)号：US20140062742A1
公开(公告)日：2014-03-06
申请号：US13882323
申请日：2012-12-27
Applicant: ASAHI KASEI MICRODEVICES CORPORATION
Inventor： Junya Nakanishi , Yutaka Nakanishi , Seiko Nakamoto
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/0656 , H03M1/12 , H03M1/1265 , H03M1/66
Abstract: An A/D converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.
Abstract translation: 一种A / D转换器，包括：采样电路，包括连续部分，采样和保持部分，用于基于从连续部分输入的模拟信号间歇地采样输入信号，以保持和传送采样信号;以及数字部分，用于输出 从采样保持部分传送的信号作为数字信号; 以及控制电路，用于提供不连续抖动的时钟信号，并将提供抖动的时钟信号提供给采样保持部。
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公开(公告)号：US08253614B1
公开(公告)日：2012-08-28
申请号：US12832352
申请日：2010-07-08
Applicant: Rajesh Tiruvuru
Inventor： Rajesh Tiruvuru
IPC: H03M1/12
CPC classification number: H03M1/0656 , H03M1/162
Abstract: Methods and systems for converting analog signals to digital signal using a cyclic analog-to-digital converter are disclosed. For example, such a cyclic analog-to-digital converter may include digitization circuitry configured to digitize either an input signal or an amplified feedback residue signal to produce first digital signals, digital accumulator circuitry configured to produce N-bits of digital information based on the first digital signals over N consecutive cycles, where N is a positive integer, and a residue amplifier configured to amplify a residue signal to produce the amplified feedback residue signal, wherein for at least M cycles, the residue amplifier operates using a capacitor averaging technique, where M is a positive integer and less than N, and wherein for P cycles the residue amplifier operates using a simple gain amplification technique, where P is a positive integer and less than N.
Abstract translation: 公开了使用循环模数转换器将模拟信号转换成数字信号的方法和系统。 例如，这种循环模数转换器可以包括被配置为数字化输入信号或放大的反馈余量信号以产生第一数字信号的数字化电路，数字累加器电路被配置为基于该数字信号产生数字信息的N位 在N个连续周期中的第一数字信号，其中N是正整数，以及残余放大器，其被配置为放大残留信号以产生放大的反馈残留信号，其中对于至少M个周期，残余放大器使用电容器平均技术进行操作， 其中M是正整数且小于N，并且其中对于P循环，残余放大器使用简单的增益放大技术操作，其中P是正整数并小于N.
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4.发明授权Increasing the SNR of successive approximation type ADCs without compromising throughput performance substantially 有权增加逐次逼近型ADC的SNR，而不会大大降低吞吐量性能公开(公告)号：US06894627B2
公开(公告)日：2005-05-17
申请号：US10663729
申请日：2003-09-17
Applicant: Seetharaman Janakiraman , Kiran Manohar Godbole , Surendranath Nagesh
Inventor： Seetharaman Janakiraman , Kiran Manohar Godbole , Surendranath Nagesh
CPC classification number: H03M1/06 , H03M1/0656 , H03M1/208
Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.
Abstract translation: 通过从相同的模拟采样产生多个N位代码并对N位代码进行平均，将模拟信号转换为N位数字码，具有高SNR（信噪比）。 然而，整个N位代码仅被确定一次，并且仅产生P位（P小于N）个代码。 可以对P位代码进行平均，并且基于平均值校正N位代码以产生精确的N位数字代码。 由于P可以远小于N，所以可以在几次迭代中实现校正，从而使得能够以高吞吐量性能实现ADC。 由于校正，也可以获得高SNR。
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公开(公告)号：US06747588B1
公开(公告)日：2004-06-08
申请号：US10248375
申请日：2003-01-15
Applicant: Jia-Jio Huang , Yi-Ping Lin
Inventor： Jia-Jio Huang , Yi-Ping Lin
IPC: H03M112
CPC classification number: H03M1/0656 , H03M1/46
Abstract: A successive approximation analog-to-digital converter is used for converting an analog input signal into a corresponding digital output signal. The successive approximation analog-to-digital converter has a successive approximation register for storing a first digital bit stream and a second digital bit stream that are related to the analog input signal, and a digital-to-analog converter for generating a first reference voltage and a second reference voltage according to the first and second digital bit streams. The digital-to-analog converter has a first voltage divider and a second voltage divider. The first voltage divider drives the first reference voltage approaching the analog input signal to establish the first digital bit stream, and the second voltage divider drives the second reference voltage approaching the analog input signal to establish the second digital bit stream. Finally, the first and second digital bit streams are averaged to generate the digital output signal.
Abstract translation: 逐次逼近模数转换器用于将模拟输入信号转换成相应的数字输出信号。 逐次逼近模数转换器具有用于存储与模拟输入信号相关的第一数字位流和第二数字位流的逐次逼近寄存器，以及用于产生第一参考电压的数 - 模转换器 以及根据第一和第二数字位流的第二参考电压。 数模转换器具有第一分压器和第二分压器。 第一分压器驱动接近模拟输入信号的第一参考电压以建立第一数字位流，并且第二分压器驱动接近模拟输入信号的第二参考电压以建立第二数字位流。 最后，对第一和第二数字比特流进行平均以产生数字输出信号。
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Patent Agency Ranking
公开(公告)号：US09998162B2
公开(公告)日：2018-06-12
申请号：US15282622
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Eshel Gordon , Sophia Maerkovich , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B1/16 , H03M1/04 , H03M1/0656 , H03M1/0695 , H03M1/144 , H03M1/145 , H03M1/36 , H03M1/466
Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
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公开(公告)号：US20180097535A1
公开(公告)日：2018-04-05
申请号：US15282622
申请日：2016-09-30
Applicant: Intel Corporation
Inventor： Eshel Gordon , Sophia Maerkovich , Ofir Degani , Hasnain Lakdawala
CPC classification number: H04B1/16 , H03M1/04 , H03M1/0656 , H03M1/0695 , H03M1/144 , H03M1/145 , H03M1/36 , H03M1/466
Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
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公开(公告)号：US20180083647A1
公开(公告)日：2018-03-22
申请号：US15714772
申请日：2017-09-25
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor： Kentaro YOSHIOKA , Masanori FURUTA , Hiroshi KUBOTA
IPC: H03M1/46
CPC classification number: H03M1/462 , H03M1/0656 , H03M1/466 , H03M1/468 , H03M1/804
Abstract: A successive approximation register (SAR) analog-to-digital converter includes a first capacitance digital-to-analog converter (CDAC), a first comparator configured to compare a voltage of an output signal from the first CDAC with a reference voltage, a first SAR circuit configured to control the first CDAC based on an output of the first comparator, a second CDAC to which the output signal from the first CDAC is input, a second comparator configured to compare a voltage of an output signal from the second CDAC with a reference voltage, a second SAR circuit configured to control the second CDAC based on an output of the second comparator and generate a digital signal representing a residual voltage of the output signal of the first CDAC, and a feedback circuit configured to delay the digital signal, generate a residual signal from the delayed digital signal, and output the residual signal to the first CDAC.
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9.发明申请CURRENT TYPE D/A CONVERTER, DELTA SIGMA MODULATOR, AND COMMUNICATIONS DEVICE 有权电流型D / A转换器，DELTA SIGMA调制器和通信设备公开(公告)号：US20160126973A1
公开(公告)日：2016-05-05
申请号：US14991368
申请日：2016-01-08
Applicant: SOCIONEXT INC.
Inventor： Yosuke Mitani , Takashi Morie , Kazuo Matsukawa , Masashi Uchida
CPC classification number: H03M3/502 , H03M1/0656 , H03M1/0863 , H03M1/742 , H03M1/745 , H03M3/464
Abstract: This D/A converter includes a plurality of D/A converter elements, each comprising current sources configured to supply output currents to output nodes, and first switches configured to control the output currents. The output nodes are connected to a capacitor section having second switches and a capacitive load. The D/A converter further includes a switch control circuit configured to control the first switches responsive to digital signals, and also control the second switches in accordance with the control of the ON/OFF state of the first switches.
Abstract translation: 该D / A转换器包括多个D / A转换器元件，每个D / A转换器元件包括被配置为向输出节点提供输出电流的电流源和被配置为控制输出电流的第一开关。 输出节点连接到具有第二开关和容性负载的电容器部分。 D / A转换器还包括开关控制电路，其被配置为响应于数字信号来控制第一开关，并且还根据第一开关的接通/断开状态的控制来控制第二开关。
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公开(公告)号：US20150042499A1
公开(公告)日：2015-02-12
申请号：US14300889
申请日：2014-06-10
Applicant: Hittite Microwave Corporation
Inventor： Oystein Moldsvor
CPC classification number: H03M1/0845 , H03M1/0643 , H03M1/0656 , H03M1/12 , H03M1/1255
Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.
Abstract translation: 模数转换器包括输入信号连接器，输出信号端口，两个或多个子ADC，以及数字信号处理块。 每个子ADC的结果由数字信号处理块用于以更高的性能输出数据。
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