公开(公告)号：US20250097598A1

公开(公告)日：2025-03-20

申请号：US18963915

申请日：2024-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungwook LIM ,  Jihun KIM

IPC: H04N25/704 ,  H04N25/11 ,  H04N25/77

Abstract: An image sensor including: a pixel array including first and second pixel groups, each of the first and second pixel groups includes of pixels arranged in rows and columns; and a row driver configured to provide transmission control signals to the pixel array, the first pixel group includes a first auto-focus (AF) pixel including photodiodes arranged in a first direction, the pixels of the first pixel group output a pixel signal through a first column line, and the second pixel group includes a second AF pixel including photodiodes arranged in a second direction perpendicular to the first direction, the pixels of the second pixel group output a pixel signal through a second column line, and the first AF pixel of the first pixel group and the second AF pixel of the second pixel group receive same transmission control signals.

公开(公告)号：US20250097595A1

公开(公告)日：2025-03-20

申请号：US18828137

申请日：2024-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joosung Moon ,  Hyukbin Kwon ,  Sungjae Byun

IPC: H04N25/532 ,  H04N25/766

Abstract: An image sensor and an image processing system. The image sensor includes a pixel array comprising a plurality of pixels, a row driver configured to generate control signals for controlling the plurality of pixels, the row driver configured to use an external voltage received from a source outside the image sensor and an internal voltage generated within the image sensor, and a voltage generator configured to generate the internal voltage, wherein the external voltage includes a first external voltage and a second external voltage, the internal voltage includes a first internal voltage and a second internal voltage, a level of the first internal voltage is higher than a level of the second internal voltage, and a level of the first external voltage is between the level of the first internal voltage and the level of the second internal voltage.

公开(公告)号：US20250096880A1

公开(公告)日：2025-03-20

申请号：US18827410

申请日：2024-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dalin Zhu ,  Emad Nader Farag ,  Eko Onggosanusi

IPC: H04B7/06 ,  H04L5/00 ,  H04W24/10 ,  H04W72/044

Abstract: Methods and apparatuses for beam measurement and reporting. A method performed by a user equipment (UE) is provided. The method includes receiving first information related to inclusion in a report of at least one first report quantity associated with a first reference signal (RS) resource and receiving second information related to at least one second RS resource. The method further includes determining, based on the first RS resource, the at least one first report quantity and determining, based on the at least one second RS resource, at least one second report quantity. The method further includes determining, based on (i) the first information and (ii) the at least one second report quantity, the report and transmitting the report.

公开(公告)号：US20250096786A1

公开(公告)日：2025-03-20

申请号：US18678867

申请日：2024-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwang KONG ,  Yeunhee HUH

IPC: H03K17/0412 ,  H02M1/08 ,  H02M3/158 ,  H03K17/16

Abstract: Provided is an auxiliary circuit configured to estimate a Miller plateau of a power transistor in a power conversion system, the auxiliary circuit including a filtering circuit electrically connected to a switching node of the power conversion system and configured to filter a voltage of the switching node, and a sensing circuit electrically connected to an output node of the filtering circuit and configured to detect whether the voltage of the switching node reaches a predetermined voltage level based on a voltage of the output node of the filtering circuit.

公开(公告)号：US20250096583A1

公开(公告)日：2025-03-20

申请号：US18965639

申请日：2024-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungwook CHOI

IPC: H02J7/00 ,  H01M10/44 ,  H01M10/46

Abstract: This electronic device may comprise: a first battery cell and a second battery cell connected in series to the first battery cell; a charging circuit configured to supply power of a first specified voltage from the outside to the first battery cell and the second battery cell; and at least one processor, comprising processing circuitry, individually and/or collectively, configured to control an overcharging protection operation voltage of the first battery cell and the second battery cell to a second specified voltage, wherein at least one processor, individually and/or collectively, is configured to; identify the voltage of the first battery cell and the voltage of the second battery cell while the first battery cell and the second battery cell are charged using the power of the first specified voltage; accumulate the number of times of overcharging protection operation for a battery cell having a voltage higher than the second specified voltage, based on at least one voltage among the voltage of the first battery cell and the voltage of the second battery cell being greater than the second specified voltage; and set an overcharging protection operation voltage for a battery cell having a voltage greater than the second specified voltage as a third specified voltage less than the second specified voltage, based on the number of times of the overcharging protection operation for the battery cell having a voltage greater than the second specified voltage reaches a specified number of times.

公开(公告)号：US20250096483A1

公开(公告)日：2025-03-20

申请号：US18970093

申请日：2024-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Elena Aleksandrovna SHEPELEVA ,  Artem Rudolfovich VILENSKIY ,  Gennadiy Alexandrovich EVTYUSHKIN ,  Anton Sergeevich LUKYANOV

IPC: H01Q21/06 ,  H01Q15/00

Abstract: The disclosure relates to radio engineering, and more specifically, to a wide scan angle antenna array. Technical result consists in expanding the scanning range, increasing the efficiency of the antenna array and reducing losses. Antenna array is provided. The antenna array includes a plurality of antenna array elements, and a metasurface disposed above the antenna array, wherein the metasurface is a dielectric layer having, on a first side thereof, conductive elements configured to reflect part of radiation of the antenna array; the distance between the antenna array and the metasurface is based on an integer number of half wavelengths, an operating wavelength of the antenna array in a medium in the space between the antenna array and the metasurface, and a predetermined scanning angle of the antenna array.

公开(公告)号：US20250096211A1

公开(公告)日：2025-03-20

申请号：US18963643

申请日：2024-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam JEONG ,  Yunhee LEE

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

公开(公告)号：US20250096184A1

公开(公告)日：2025-03-20

申请号：US18653734

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan KIM

IPC: H01L23/00 ,  H01L23/373 ,  H01L25/065

Abstract: A chip bonding film is provided and includes an adhesive film layer that is curable by heat, and fillers that are thermally conductive and are contained in the adhesive film layer, each of the fillers including magnetic particles, wherein a heat dissipation path is formed by the fillers in a vertical direction from a lower surface to an upper surface of the adhesive film layer.

公开(公告)号：US20250096158A1

公开(公告)日：2025-03-20

申请号：US18966367

申请日：2024-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538

Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

公开(公告)号：US20250096099A1

公开(公告)日：2025-03-20

申请号：US18751036

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAESUN KIM ,  HEEYOUB KANG ,  EUNKYEONG PARK ,  YISEUL HAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package may include a lower redistribution structure having a lower redistribution layer, a lower chip structure on the lower redistribution structure, the lower chip structure including a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a plurality of first posts on a side of the second semiconductor chip and electrically connected to the first semiconductor chip, and a first encapsulant covering the first semiconductor chip, the second semiconductor chip, and the plurality of first posts, a plurality of second posts on a side of the lower chip structure and electrically connected to the lower redistribution layer, a second encapsulant covering the lower chip structure and each of the plurality of second posts, connection vias passing through a portion of the second encapsulant, and electrically connected to the plurality of first posts, and an upper redistribution structure on the second encapsulant.