公开(公告)号：US20240055335A1

公开(公告)日：2024-02-15

申请号：US18134314

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook PARK ,  Sangkyu KIM ,  Yoonseok SEO ,  Sangnam JEONG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L23/49816 ,  H01L23/5383 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73

Abstract: Provided is a semiconductor package including a base substrate, and a first package and a second package mounted apart from each other on an upper surface of the base substrate in a horizontal direction, wherein the second package includes, on each surface thereof, connection pads corresponding to a package ball map including cells, arranged in a plurality of rows and a plurality of columns, each of which has one signal arranged therein, wherein the package ball map includes a first signal, or a data signal, arranged in at least some cells among the cells of the package ball map, and a second signal, or a command or address signal, and the first signal is arranged apart from the second signal.

公开(公告)号：US20230260889A1

公开(公告)日：2023-08-17

申请号：US18110472

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： Sangnam JEONG ,  Sangsub Song

IPC: H01L23/498 ,  H10B80/00 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H05K1/181 ,  H10B80/00 ,  H01L24/16

Abstract: A semiconductor package includes: a package substrate including a plurality of insulating layers and a plurality of metal pattern layers respectively disposed on the plurality of insulating layers, wherein each of the plurality of metal pattern layers has an interconnection layer; at least one semiconductor chip disposed on an upper surface of the package substrate, and connected to the interconnection layer; contact pads disposed on a lower surface of the package substrate, and connected to the interconnection layer; and non-contact pads disposed on the lower surface of the package substrate, and insulated from the interconnection layer, wherein a lowermost metal pattern layer among the plurality of metal pattern layers has a first open region at least partially overlapping at least one non-contact pad among the non-contact pads, in a direction perpendicular to the upper surface of the package substrate.

公开(公告)号：US20250096211A1

公开(公告)日：2025-03-20

申请号：US18963643

申请日：2024-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam JEONG ,  Yunhee LEE

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

公开(公告)号：US20180366456A1

公开(公告)日：2018-12-20

申请号：US15867686

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam JEONG ,  IlJoon Kim ,  SunWon KANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/522 ,  H01L23/48

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.

公开(公告)号：US20230253381A1

公开(公告)日：2023-08-10

申请号：US17947113

申请日：2022-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam JEONG ,  Yunhee LEE

IPC: H01L25/16 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L25/162 ,  H01L23/49833 ,  H01L25/0657

Abstract: Provided are an integrated voltage regulator (IVR) package with a minimized size including one or more inductors and one or more capacitors together with an IVR chip and improving characteristics of a voltage regulator (VR), and an IVR system package including the IVR package. The IVR package includes a package substrate, a stacked structure mounted on the package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked, and an intermediate substrate disposed on the package substrate in a structure surrounding the stacked structure, the intermediate substrate including vias therein. The one or more inductors are included in the stacked structure or the intermediate substrate.

公开(公告)号：US20190295999A1

公开(公告)日：2019-09-26

申请号：US16438430

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangnam JEONG ,  IlJoon KIM ,  SunWon KANG

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.