公开(公告)号：US20110239080A1

公开(公告)日：2011-09-29

申请号：US13039961

申请日：2011-03-03

申请人： Kenji SAKAUE ,  Tatsuyuki ISHIKAWA ,  Yukio ISHIKAWA ,  Kazuhiro ICHIKAWA ,  Hironori UCHIKAWA

发明人： Kenji SAKAUE ,  Tatsuyuki ISHIKAWA ,  Yukio ISHIKAWA ,  Kazuhiro ICHIKAWA ,  Hironori UCHIKAWA

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1188

摘要： An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability β in association with each first address, a check node storage section that stores TMEM variables to calculate an external value α in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

摘要翻译： 根据实施例的LDPC错误检测/校正电路包括：选择器，其基于包括具有大小为p和移位块的单位矩阵组成的块的校验矩阵H将数据划分为p组;选择器，将组划分成Y个子组 ，存储LMEM变量以计算概率＆bgr的位节点存储部分; 与每个第一地址相关联的校验节点存储部分，其存储TMEM变量以计算与每个第二地址相关联的外部值α;旋转器，其基于移位值以旋转值对TMEM进行旋转处理;以及 （p / Y）操作单元组成的运行电路，以子组为单位执行并行处理。

公开(公告)号：US20110219284A1

公开(公告)日：2011-09-08

申请号：US12848476

申请日：2010-08-02

申请人： Hironori Uchikawa ,  Yoshihisa Kondo

发明人： Hironori Uchikawa ,  Yoshihisa Kondo

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/10 ,  H03M13/05 ,  Y02D10/13

摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

摘要翻译： 非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。 半导体存储器存储用LDPC码编码的数据帧。 所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。 所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。 所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

公开(公告)号：US07639753B2

公开(公告)日：2009-12-29

申请号：US11385835

申请日：2006-03-22

申请人： Hironori Uchikawa ,  Kohsuke Harada

发明人： Hironori Uchikawa ,  Kohsuke Harada

IPC分类号： H04B7/02

CPC分类号： H04L1/005 ,  H04L1/0057

摘要： Receiving-apparatus employed in MIMO-system includes space-filtering-unit configured to separate receive-signals to signal of first-data-sequence and signal of second-data-sequence on basis of estimation result, provisional-decoding-unit configured to LDPC-decode signal of first-data-sequence and signal of second-data-sequence with check-matrices which is modified in different-forms by fundamental-row-operation from each other, to obtain provisional-likelihood-ratio for first-data-sequence and second-data-sequence, provisional-output-unit configured to output provisional-first-data-sequence and provisional-second-data-sequence on the basis of provisional-likelihood-ratio for first-data-sequence and second-data-sequence respectively, replica-signal-generation-unit configured to generate replica-signal, on basis of provisional-first-data-sequence and provisional-second-data-sequence and estimation-result of propagation-path-estimation-unit, soft-decision-outputting-unit configured to obtain receive-likelihood-values of first-data-sequence and second-data-sequence, on basis of residual-signal obtained by subtracting replica-signal from receive-signals, actual-decoding-unit configured to LDPC-decode receive-likelihood-values, by using the check-matrices, to obtain likelihood-ratio of first-data-sequence and likelihood-ratio of second-data-sequence, and actual-output-unit configured to obtain first-data-sequence and second-data-sequence on the basis of likelihood-ratio of first-data-sequence generated by the actual-decoding-unit and likelihood-ratio of second-data-sequence to hard-decision.

摘要翻译： 在MIMO系统中采用的接收装置包括空间滤波单元，其被配置为基于估计结果将接收信号分离为第一数据序列的信号和第二数据序列的信号，临时解码单元被配置为LDPC - 第一数据序列的解码信号和具有通过基本行操作以不同形式修改的校验矩阵的第二数据序列的信号，以获得第一数据序列的第一数据序列的临时似然比， 序列和第二数据序列临时输出单元，被配置为基于第一数据序列和第二数据的临时似然比输出临时第一数据序列和临时第二数据序列 分别基于临时第一数据序列和临时第二数据序列以及传播路径估计单元的估计结果，配置为生成副本信号的复制信号生成单元，软 - 确定输出单元配置为obt 基于通过从接收信号中减去副本信号而获得的残差信号，对第一数据序列和第二数据序列的接收似然值进行解码，实现解码单元被配置为LDPC解码接收似然值， 通过使用校验矩阵来获得第一数据序列和第二数据序列的似然比的似然比以及被配置为获得第一数据序列和第二数据序列的实际输出单元的值， 基于由实际解码单元生成的第一数据序列的似然比和第二数据序列的似然比与硬判决的顺序。

公开(公告)号：US20080005641A1

公开(公告)日：2008-01-03

申请号：US11723336

申请日：2007-03-19

申请人： Hironori Uchikawa ,  Kohsuke Harada

发明人： Hironori Uchikawa ,  Kohsuke Harada

IPC分类号： H03M13/00

CPC分类号： H03M13/114 ,  H03M13/616 ,  H03M13/6362

摘要： A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits, the data-bits and the parity-bits included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix, a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods, a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities, an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix, a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit, and a checking-unit configured to execute parity check of a discrimination result of the discriminating-unit, to obtain the code data.

摘要翻译： 解码器被配置为包括：获取单元，被配置为获取奇偶校验比特的第一各自的似然性和奇偶校验比特的第二相应似然性，数据比特和奇偶校验比特包括在通过LDPC编码获得的代码数据中， 具有低密度奇偶校验矩阵的比特，检测单元，被配置为检测第一各个似然性和第二各自似然性的可靠性;形成单元，被配置为形成表示更新第一和第二各自可能性的顺序的更新计划， 根据可靠性增加的顺序，更新单元被配置为利用低密度奇偶校验矩阵以由更新调度表示的顺序更新第一和第二各自的可能性;鉴别单元，被配置为执行硬判决 由更新单元更新的可能性;以及检查单元，被配置为执行对判别结果o的奇偶校验 f鉴别单元，以获得代码数据。