公开(公告)号：US20120066563A1

公开(公告)日：2012-03-15

申请号：US13043918

申请日：2011-03-09

申请人： Haruka OBATA ,  Hironori Uchikawa

发明人： Haruka OBATA ,  Hironori Uchikawa

IPC分类号： H03M13/05

CPC分类号： H03M13/658 ,  H03M13/1111 ,  H03M13/112 ,  H03M13/1128 ,  H03M13/6583

摘要： According to an embodiment, an error correction decoder carries out iterative decoding for data coded using an irregular LDPC code. The decoder includes a likelihood control unit. The likelihood control unit is configured to carry out weighting using first extrinsic value weights when a first condition including a condition that a code word cannot be obtained even when number of times the iterative decoding has been carried out is greater than a first iterative times, in order to increase absolute value of a extrinsic value from a check node not satisfying a parity check to a variable node, wherein the first extrinsic value weights are equal to each other or become larger in descending order of column weights of the variable nodes, and a maximum of the first extrinsic value weights is not equal to a minimum of the first extrinsic value weights.

摘要翻译： 根据实施例，纠错解码器对使用不规则LDPC码编码的数据进行迭代解码。 解码器包括可能性控制单元。 似然度控制单元被配置为，在包括即使执行迭代解码的次数大于第一迭代次数的情况下也不能获得代码字的条件的第一条件下，使用第一非本征值权重进行加权， 为了从不满足奇偶校验的校验节点向变量节点增加非本征值的绝对值，其中，第一非本征值权重彼此相等，或者以可变节点的列权重的降序变大，并且 第一非本征值权重的最大值不等于第一外在值权重的最小值。

公开(公告)号：US07979777B2

公开(公告)日：2011-07-12

申请号：US11723336

申请日：2007-03-19

申请人： Hironori Uchikawa ,  Kohsuke Harada

发明人： Hironori Uchikawa ,  Kohsuke Harada

IPC分类号： H03M13/00

CPC分类号： H03M13/114 ,  H03M13/616 ,  H03M13/6362

摘要： A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits. The data-bits and the parity-bits are included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix. The decoder also includes a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods. The decoder also includes a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities. The decoder also includes an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix. The decoder also includes a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit. The decoder also includes a checking-unit configured to execute parity check of a discrimination result of the discriminating-unit, to obtain the code data.

摘要翻译： 解码器被配置为包括被配置为获取奇偶校验位的数据位和第二相应似然性的第一各自似然性的获取单元。 数据位和奇偶校验位包含在通过对具有低密度奇偶校验矩阵的数据位进行LDPC编码而获得的代码数据中。 解码器还包括被配置为检测第一各自的可能性和第二各自似然性的可靠性的检测单元。 解码器还包括形成单元，其被配置为根据可靠性形成表示更新第一和第二各个似然性的顺序的更新调度，以便增加可靠性。 解码器还包括更新单元，其被配置为利用低密度奇偶校验矩阵来以由更新调度表示的顺序来更新第一和第二各自的似然性。 解码器还包括被配置为执行由更新单元更新的可能性的硬判决的鉴别单元。 解码器还包括一个检查单元，被配置为执行鉴别单元的鉴别结果的奇偶校验，以获得代码数据。

公开(公告)号：US20110038212A1

公开(公告)日：2011-02-17

申请号：US12715772

申请日：2010-03-02

申请人： Hironori Uchikawa ,  Kenji Sakurada

发明人： Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C16/34

摘要： A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.

摘要翻译： 控制器包括：生成单元，被配置为将存储单元中保持的第二阈值电压电平与预定的第三阈值电压电平之间的比较结果进行聚合，并生成第二阈值电压电平的直方图;估计单元，被配置为估计分布的统计参数 基于所述直方图，根据写入数据相对于第一阈值电压电平的第二阈值电压电平，以及确定单元，被配置为确定第五阈值电压电平，所述第五阈值电压电平定义指示读取结果的第四阈值电压电平的边界 基于所述统计参数从所述第三阈值电压电平的所述存储器单元，使得所述第一阈值电压电平和所述第四阈值电压电平之间的相互信息量变为最大。

公开(公告)号：US07872910B2

公开(公告)日：2011-01-18

申请号：US12397369

申请日：2009-03-04

申请人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

发明人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C2211/5646

摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

摘要翻译： 在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。 位线控制电路连接到位线以控制位线。 字线控制电路将多位数据读取电压作为字线电压施加到字线。 多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。 此外，它将软值读取电压作为字线电压施加到字线。 软值读取电压小于阈值电压分布的上限并且大于其下限。 似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

公开(公告)号：US20090183052A1

公开(公告)日：2009-07-16

申请号：US12404861

申请日：2009-03-16

申请人： Shinichi KANNO ,  Hironori Uchikawa

发明人： Shinichi KANNO ,  Hironori Uchikawa

IPC分类号： H03M13/05 ,  G06F11/22 ,  G06F11/07

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

摘要翻译： 半导体存储器件包括多个检测码发生器，其被配置为分别产生多个检测码以分别检测多个数据项中的错误;多个第一校正码发生器，被配置为产生多个第一校正码以校正错误 在多个第一数据块中，分别包含数据项之一和相应检测码的第一数据块，被配置为生成用于校正第二数据块中的错误的第二校正码的第二校正码发生器， 包含第一数据块的第二数据块，以及被配置为非易失性地存储第二数据块，第一校正码和第二校正码的半导体存储器。

公开(公告)号：US20080301532A1

公开(公告)日：2008-12-04

申请号：US11860015

申请日：2007-09-24

申请人： Hironori UCHIKAWA ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

发明人： Hironori UCHIKAWA ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C29/52 ,  G06F11/1072 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5641 ,  G11C2211/5643

摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储N位（N> = 2）的信息而排列的多个存储单元。 奇偶校验数据加法器电路将用于纠错的奇偶校验数据添加到要存储在存储单元阵列中的每个特定数据位。 帧转换器电路将包含数据位和奇偶校验数据的帧数据均匀地分割成N个子帧数据。 编程电路将分割成N个的子帧数据存储在对应于N位信息的N个子页中。

公开(公告)号：US20080205540A1

公开(公告)日：2008-08-28

申请号：US12106101

申请日：2008-04-18

申请人： Daisuke TAKEDA ,  Yoshimasa EGASHIRA ,  Tsuguhide AOKI ,  Yasuhiko TANABE ,  Kohsuke HARADA ,  Hironori UCHIKAWA

发明人： Daisuke TAKEDA ,  Yoshimasa EGASHIRA ,  Tsuguhide AOKI ,  Yasuhiko TANABE ,  Kohsuke HARADA ,  Hironori UCHIKAWA

IPC分类号： H04L1/02

CPC分类号： H04B7/04 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0226

摘要： Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have different subcarrier arrangements.

摘要翻译： 在从多个天线发送数据之前，从这些天线发送多个已知符号序列。 每个已知符号序列包含具有不同副载波布置的多个已知符号。 从不同天线发送的已知符号具有不同的子载波布置。

公开(公告)号：US20080104459A1

公开(公告)日：2008-05-01

申请号：US11877287

申请日：2007-10-23

申请人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

发明人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

IPC分类号： G06F11/26

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。 似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。 错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。 似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

公开(公告)号：US20190259458A1

公开(公告)日：2019-08-22

申请号：US16123162

申请日：2018-09-06

申请人： Noboru SHIBATA ,  Hironori UCHIKAWA

发明人： Noboru SHIBATA ,  Hironori UCHIKAWA

IPC分类号： G11C16/26 ,  H01L27/11582 ,  H01L27/1157 ,  G11C7/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04

摘要： According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

公开(公告)号：US20130151921A1

公开(公告)日：2013-06-13

申请号：US13706663

申请日：2012-12-06

申请人： Hironori UCHIKAWA ,  Haruka OBATA

发明人： Hironori UCHIKAWA ,  Haruka OBATA

IPC分类号： H03M13/13

CPC分类号： H03M13/13 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

摘要： According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns.

摘要翻译： 根据一个实施例，编码装置包括输入单元和生成单元。 输入单元输入包含q（N-J）个符号（q，J和N是整数N> J）的数据符号序列。 生成单元通过将包含qJ个符号的奇偶校验符号序列添加到数据符号序列来生成包含qN符号的码字。 码字满足qJ行×qN列的奇偶校验矩阵的奇偶校验方程。 对应于奇偶校验矩阵中的奇偶校验符号序列的qJ行×qJ列的第一子矩阵包括第二子矩阵。 第二子矩阵包括qL行×qL列（L是整数J> L）和q（J-L）行×qL列的第一非零矩阵的第一单位矩阵。