公开(公告)号：US5202277A

公开(公告)日：1993-04-13

申请号：US918933

申请日：1992-07-22

申请人： Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

发明人： Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28114

摘要： A method of fabricating a semiconductor device having gate-drain overlap MOSFETs in which side surfaces of upper portions of gate lines are anisotropically etched using a buffer film as an etch stop is disclosed. An insulating film as a gate insulator is formed on a semiconductor layer of a first conductivity type. A first conductive film is formed on the gate insulator. A buffer film having openings in gate line regions is formed on the first conductive film. A second conductive film is formed on the buffer film. The second conductive film is patterned into wiring shape to form upper portions of gate lines covering the openings of the buffer film. Ions of a second conductivity type are implanted into the semiconductor layer using the upper portions of the gate lines as an implant mask to form sources and drains in the semiconductor layer. Sidewall spacers are formed on the sides of the upper portions of the gate lines. The buffer film and the first conductive film are etched using the upper portions of the gate lines and the sidewall spacers as an etching mask to form under portions of the gate lines.

摘要翻译： 公开了一种制造具有栅极 - 漏极重叠MOSFET的半导体器件的方法，其中栅极线的上部的侧表面使用缓冲膜作为蚀刻停止点进行各向异性蚀刻。 作为栅极绝缘体的绝缘膜形成在第一导电类型的半导体层上。 在栅极绝缘体上形成第一导电膜。 在第一导电膜上形成在栅线区域具有开口的缓冲膜。 在缓冲膜上形成第二导电膜。 将第二导电膜图案化成布线形状，以形成覆盖缓冲膜的开口的栅极线的上部。 使用栅极线的上部作为注入掩模将第二导电类型的离子注入到半导体层中，以在半导体层中形成源极和漏极。 侧壁间隔件形成在栅极线的上部的侧面上。 使用栅极线和侧壁间隔物的上部作为蚀刻掩模蚀刻缓冲膜和第一导电膜，以在栅极线的一部分形成。