公开(公告)号：US4965511A

公开(公告)日：1990-10-23

申请号：US370046

申请日：1989-06-22

申请人： Akira Nishimura ,  Yasuyuki Nozuyama

发明人： Akira Nishimura ,  Yasuyuki Nozuyama

IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/267

CPC分类号： G06F11/2226 ,  G01R31/318536

摘要： A test circuit targeted to test data path blocks such as an arithmetic block to be tested including an arithmetic unit for operating multiple bits as well as including various registers related to the arithmetic unit. The test circuit includes flip-flops for receiving data from a first pin forming a shift register, having the ability of holding data by the control of a test node signal multiplexers for selectively generating control signals for controlling the elements in the data path block to be tested, a second pin connected to the flip-flops and multiplexers to externally provide them with a test mode signal under a test mode, a bus switch connected between a third pin and an internal data bus to control input of test data from the third pin to the arithmetic block and input of an operation result to the third pin via the internal data bus, gates for controlling data input and output with respect to the bus switch, and a timing signal generator for generating timing signals for controlling the gates. At the time of test, the second pin provides the test mode signal. According to this signal, the flip-flops hold test control data, while the multiplexers generate control signals based on the timing signals to test the arithmetic block at high speed.