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121 条记录 (耗时 0.034 秒)

    System and method for statistical timing analysis of digital circuits
    51.
    发明授权
    System and method for statistical timing analysis of digital circuits 有权
    数字电路统计时序分析的系统和方法

    公开(公告)号：US08010921B2

    公开(公告)日：2011-08-30

    申请号：US12209461

    申请日：2008-09-12

    申请人： Chandramouli Visweswariah

    发明人： Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： The present invention is a system and method for statistical or probabilistic static timing analysis of digital circuits, taking into account statistical delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Arrival times and required arrival times are propagated as parameterized random variables while taking correlations into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The timing analysis complexity is linear in the size of the graph and the number of sources of variation. The result is a timing report in which all timing quantities such as arrival times and slacks are reported as probability distributions in a parameterized form.

    摘要翻译： 本发明是考虑到统计延迟变化的数字电路的统计或概率静态时序分析的系统和方法。 假设每个门或线的延迟由标称部分，由每个变化源参数化的相关随机部分和独立的随机部分组成。 考虑到相关性，到达时间和所需到达时间作为参数化随机变量传播。 包括早期模式和晚期模式时序; 处理组合和顺序电路; 静态CMOS以及动态逻辑系列。 时间分析复杂度在图形的大小和变异的数量上是线性的。 结果是定时报告，其中所有定时量（如到达时间和休息）以参数化形式报告为概率分布。

    ORDERING OF STATISTICAL CORRELATED QUANTITIES
    52.
    发明申请
    ORDERING OF STATISTICAL CORRELATED QUANTITIES 有权
    统计相关数量的订购

    公开(公告)号：US20110191730A1

    公开(公告)日：2011-08-04

    申请号：US12696186

    申请日：2010-01-29

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.

    摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

    Yield Computation and Optimization for Selective Voltage Binning
    53.
    发明申请
    Yield Computation and Optimization for Selective Voltage Binning 有权
    选择电压分级的产量计算和优化

    公开(公告)号：US20110106497A1

    公开(公告)日：2011-05-05

    申请号：US12610291

    申请日：2009-10-31

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G21C17/00

    CPC分类号： G06F17/5045 ,  G06F2217/10 ,  G06F2217/82

    摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.

    摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一个方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。

    Method and apparatus for incrementally computing criticality and yield gradient
    54.
    发明授权
    Method and apparatus for incrementally computing criticality and yield gradient 有权
    递增计算临界和屈服梯度的方法和装置

    公开(公告)号：US07861199B2

    公开(公告)日：2010-12-28

    申请号：US11870672

    申请日：2007-10-11

    申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at least one diagnostic entity, and computing a diagnostic metric relating to the diagnostic entity(ies) from the chip slack and the slack of the diagnostic entity(ies).

    摘要翻译： 在一个实施例中，本发明是用于递增地计算临界度和屈服梯度的方法和装置。 用于计算电路的诊断度量的方法的一个实施例包括将电路建模为定时图，确定电路的芯片松弛，确定至少一个诊断实体的松弛，以及计算与诊断实体有关的诊断度量 （ies）从芯片松弛和诊断实体的松弛。

    Methods for conserving memory in statistical static timing analysis
    55.
    发明授权
    Methods for conserving memory in statistical static timing analysis 有权
    统计静态时序分析中保存记忆的方法

    公开(公告)号：US07849429B2

    公开(公告)日：2010-12-07

    申请号：US12053887

    申请日：2008-03-24

    申请人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031

    摘要： A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.

    摘要翻译： 在统计静态时序分析中提供了一种用于存储器保存的方法。 在统计静态时序分析程序中使用时序运行创建时序图。 识别作为部分存储和约束点的候选的定时图中的多个节点。 定时数据被持久存储在约束点。 从约束点检索持续定时数据，并用于在定时分析期间计算多个节点处的中间定时数据。

    Method and apparatus for static timing analysis in the presence of a coupling event and process variation
    59.
    发明授权
    Method and apparatus for static timing analysis in the presence of a coupling event and process variation 失效
    在存在耦合事件和过程变化的情况下进行静态时序分析的方法和装置

    公开(公告)号：US07739640B2

    公开(公告)日：2010-06-15

    申请号：US11622979

    申请日：2007-01-12

    申请人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    发明人： Soroush Abbaspour ,  Gregory M. Schaeffer ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.

    摘要翻译： 在一个实施例中，本发明是在存在耦合事件和过程变化的情况下用于静态时序分析的方法和装置。 用于计算由于集成电路设计中的两个相邻网络之间的耦合事件而导致的延迟和转换的统计变化的方法的一个实施例包括进行集成电路设计的统计时序分析，计算相邻网络之间的统计重叠窗口， 其中统计定时窗口表示相邻网络上的信号可以同时切换的时间段，并且根据统计重叠窗口计算由于耦合事件引起的延迟的统计变化。