公开(公告)号：US06728912B2

公开(公告)日：2004-04-27

申请号：US09833724

申请日：2001-04-12

申请人： James W. Dawson ,  Paul A. Bunce ,  Donald W. Plass

发明人： James W. Dawson ,  Paul A. Bunce ,  Donald W. Plass

IPC分类号： G11C2900

CPC分类号： G11C29/12 ,  G11C8/08 ,  G11C29/34

摘要： A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.

摘要翻译： 用于测试SOI技术存储器电路（例如SRAM）中用于弱SOI单元的方法使用具有字线脉冲宽度控制电路的复位测试电路，该电路可以在没有性能影响的情况下实现，并允许使用未使用的硅来最小化区域使用影响并允许 使用测试复位电路筛选用于弱SOI单元的集成SOI存储器阵列电路，以便在正常时间存储单元位选择和写入信号关断以压缩单元写入裕度时选择性地将字线脉冲宽度改变为减小的时间。 此外，在测试期间，可以通过将复位路径测试电路的复位信号阻塞到字路径来延长字线脉冲宽度，以产生比正常脉冲宽度更长的字线。 此外，在正常操作的测试期间，允许复位信号通过复位测试电路的通过门极复用器。

公开(公告)号：US4901279A

公开(公告)日：1990-02-13

申请号：US208719

申请日：1988-06-20

申请人： Donald W. Plass

发明人： Donald W. Plass

IPC分类号： G11C11/41 ,  G11C11/417 ,  H01L27/10 ,  H01L27/11

CPC分类号： G11C11/417 ,  H01L27/1104

摘要： A static random access memory cell implemented with metal Schottky field-effect transistors. The cell has first and second branches, each of the branches including: a depletion mode current limiting transistor having a drain connected to a first circuit node; a depletion mode load transistor having a drain connected to the source of the current limiting transistor and a source connected to a second circuit node; an enhancement mode active transistor having a drain connected to the second circuit node and a source connected to a third circuit node; an enhancement mode access transistor having a source connected to the second circuit node and a gate connected to the gate of the current limiting transistor; the gate of the load transistor connected to the second circuit node; the commonly connected gates of the current limiting transistor and the access transistor adapted to receive a word-line signal; and the drain of the access transistor adapted to receive a bit-line signal. The first circuit node is adapted for connection to a source of bias voltage, and the third circuit node is adapted for connection to a circuit ground. The first and second branches are cross-connected between the second nodes and the gates of the active transistors.