公开(公告)号：US20090094414A1

公开(公告)日：2009-04-09

申请号：US12333320

申请日：2008-12-12

申请人： Chi-Chun Hsu ,  Wen-Yi Wu

发明人： Chi-Chun Hsu ,  Wen-Yi Wu

IPC分类号： G06F12/00 ,  G06F9/44

CPC分类号： G06F8/65

摘要： A storage device includes a firmware memory, a buffer memory, a processor and a memory update controller. When the storage device is under a normal mode, the memory update controller is in an idle state. The processor controls the storage device to fetch an update firmware and store the update firmware into the buffer memory. When the storage device is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

摘要翻译： 存储装置包括固件存储器，缓冲存储器，处理器和存储器更新控制器。 当存储设备处于正常模式时，存储器更新控制器处于空闲状态。 处理器控制存储设备获取更新固件并将更新固件存储到缓冲存储器中。 当存储设备处于固件更新模式时，处理器处于空闲状态。 存储器更新控制器从缓冲存储器中获取更新固件，并且将更新固件存储在固件存储器中，而处理器不执行更新程序代码。

公开(公告)号：US07480224B2

公开(公告)日：2009-01-20

申请号：US11212084

申请日：2005-08-24

申请人： Wen-Yi Wu ,  Meng-Ta Yang

发明人： Wen-Yi Wu ,  Meng-Ta Yang

IPC分类号： G11B7/00

CPC分类号： G11B20/18

摘要： The invention discloses a decoding apparatus and the method thereof for decoding a signal retrieved by an optical information reproducing system from an optical information recording medium. N legal codes are predetermined. According to the invention, first, the retrieved signal is converted into a data stream. Then, in a Viterbi decoding manner, the data stream is decoded into a digital code in accordance with a level of the data stream and N reference levels. Then, the binary code is decoded by a binary array into one of the N legal codes, and each of the N legal codes corresponds to one of N reference levels. In particular, the N reference levels are corrected by various detected conditions to enhance the correctness of decoded data.

摘要翻译： 本发明公开了一种解码装置及其方法，用于从光学信息记录介质解码由光学信息再现系统检索的信号。 N个法定代码是预先确定的。 根据本发明，首先，将检索到的信号转换为数据流。 然后，以维特比解码的方式，根据数据流的电平和N个参考电平将数据流解码成数字码。 然后，二进制码由二进制数组解码为N个合法码之一，N个合法码中的每一个对应于N个参考电平之一。 特别地，通过各种检测条件来校正N个参考电平，以增强解码数据的正确性。

公开(公告)号：US07454691B2

公开(公告)日：2008-11-18

申请号：US11582598

申请日：2006-10-17

申请人： Li-Lien Lin ,  Wen-Yi Wu

发明人： Li-Lien Lin ,  Wen-Yi Wu

IPC分类号： H03M13/00

CPC分类号： H03M13/2903 ,  G11B20/00086 ,  G11B20/1833 ,  G11B20/1866 ,  H03M13/2906

摘要： The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

摘要翻译： 本发明是用于对数字数据进行编码的方法和系统。 编码系统进行计算错误检测码的步骤和同时加扰主数据的步骤，以减少访问第一存储器的时间。 本发明包括第二存储器。 编码系统每次可以访问多个记录列，这进一步减少了访问第一个内存的时间。

公开(公告)号：US07434140B2

公开(公告)日：2008-10-07

申请号：US11042085

申请日：2005-01-26

申请人： Li-Lien Lin ,  Wen-Yi Wu

发明人： Li-Lien Lin ,  Wen-Yi Wu

IPC分类号： H03M13/00

CPC分类号： G11B20/1217 ,  G11B20/18 ,  G11B2020/1222 ,  G11B2020/1272 ,  G11B2020/1294 ,  G11B2220/2537 ,  G11B2220/2541

摘要： An apparatus for accessing and transferring optical data has a memory supporting the page-mode function, an accessing device used to access an error correction block from the optical storage medium and store it into the memory to make the portion of data in the same column of the error correction block stored in a particular locality greater than the portion of data in the same row of the error correction block stored in the particular locality, and an error correction decoder used to access the data of the error correction block to perform the error correction process. The apparatus uses the feature of the DRAM, such as page-mode function, and the data arrangement of the memory to improve the access efficiency of the memory. The apparatus can thus increase the access speed of the error correction decoder and improve the accessing efficiency.

摘要翻译： 用于访问和传送光学数据的设备具有支持页面模式功能的存储器，用于从光存储介质访问错误校正块并将其存储到存储器中的访问设备，以使数据的同一列中的数据部分 存储在大于存储在特定地点的纠错块的同一行中的数据部分的特定位置的纠错块以及用于访问纠错块的数据以执行纠错的纠错解码器 处理。 该装置使用DRAM的特征，例如页面模式功能，以及存储器的数据排列，以提高存储器的访问效率。 因此，该装置可以增加纠错解码器的访问速度并提高访问效率。

公开(公告)号：US07289410B2

公开(公告)日：2007-10-30

申请号：US10623576

申请日：2003-07-22

申请人： Hao-Cheng Chen ,  Wen-Yi Wu

发明人： Hao-Cheng Chen ,  Wen-Yi Wu

IPC分类号： G11B7/00

CPC分类号： G11B7/0053

摘要： An ADIP demodulation method and apparatus, which are used in an optical disk driver to generate the ADIP information according to a wobble signal. The apparatus includes a slicing unit for receiving the wobble signal and generating a wobble pulse, a phase locked loop for generating a reference wobble signal with the same frequency and phase as the wobble pulse and a reference clock with frequency higher than the wobble pulse, a channel bit generator for generating a channel bit signal according to the reference wobble signal and the wobble pulse, and a decoder for decoding to ADIP information according to the channel bit signal. The channel bit generator generates a difference signal between the wobble pulse and the reference wobble signal, and outputs the channel bit signal according to the difference signal.

摘要翻译： 一种ADIP解调方法和装置，用于光盘驱动器中以根据摆动信号产生ADIP信息。 该装置包括用于接收摆动信号并产生摆动脉冲的切片单元，用于产生具有与摆动脉冲相同的频率和相位的参考摆动信号和频率高于摆动脉冲的参考时钟的锁相环， 信道位发生器，用于根据参考摆动信号和摆动脉冲产生信道位信号;以及解码器，用于根据信道位信号对ADIP信息进行解码。 通道位发生器产生摆动脉冲与参考摆动信号之间的差分信号，并根据差分信号输出通道位信号。

公开(公告)号：US07139962B2

公开(公告)日：2006-11-21

申请号：US10409454

申请日：2003-04-09

申请人： Li-Lien Lin ,  Wen-Yi Wu

发明人： Li-Lien Lin ,  Wen-Yi Wu

IPC分类号： H03M13/00

CPC分类号： H03M13/2903 ,  G11B20/00086 ,  G11B20/1833 ,  G11B20/1866 ,  H03M13/2906

摘要： The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

摘要翻译： 本发明是用于对数字数据进行编码的方法和系统。 编码系统进行计算错误检测码的步骤和同时加扰主数据的步骤，以减少访问第一存储器的时间。 本发明包括第二存储器。 编码系统每次可以访问多个记录列，这进一步减少了访问第一个内存的时间。

公开(公告)号：US20060059300A1

公开(公告)日：2006-03-16

申请号：US10907949

申请日：2005-04-21

申请人： Chi-Chun Hsu ,  Wen-Yi Wu

发明人： Chi-Chun Hsu ,  Wen-Yi Wu

IPC分类号： G06F12/00 ,  G06F9/44

CPC分类号： G06F8/65

摘要： The present invention discloses an optical disc drive capable of updating firmware, and firmware update method thereof. The disclosed optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

摘要翻译： 本发明公开了一种能够更新固件的光盘驱动器及其固件更新方法。 所公开的光盘驱动器包括固件存储器，缓冲存储器和系统控制芯片。 系统控制芯片包括处理器和存储器更新控制器。 当光盘驱动器处于正常模式时，存储器更新控制器处于空闲状态。 处理器控制光盘驱动器从光盘获取更新固件，并将更新固件存储到缓冲存储器中。 当光盘驱动器处于固件更新模式时，处理器处于空闲状态。 存储器更新控制器从缓冲存储器中获取更新固件，并且将更新固件存储在固件存储器中，而处理器不执行更新程序代码。

公开(公告)号：US5781927A

公开(公告)日：1998-07-14

申请号：US593804

申请日：1996-01-30

申请人： Wen-Yi Wu ,  Gene Yang

发明人： Wen-Yi Wu ,  Gene Yang

IPC分类号： G06F13/18 ,  G06F13/00 ,  G06F13/366

CPC分类号： G06F13/18

摘要： A main memory arbitration arrangement for a computer system. It features the ability to set priorities between a main system and peripheral system to optimize system efficiency. The arbitration arrangement comprises a main memory controller and a peripheral system. The main memory controller has ports for issuing memory request signals of various priority levels determined based on urgency of the need for the main memory. The main memory controller will determine whether to yield the control of the main memory to the peripheral system based on the priority level of the memory request signal received and the urgency of the current operating condition of the main system. The result is the enhancing of the overall efficiency of the computer system.

摘要翻译： 用于计算机系统的主存储器仲裁装置。 它具有在主系统和外围系统之间设置优先级以优化系统效率的能力。 仲裁装置包括主存储器控制器和外围系统。 主存储器控制器具有用于发出基于对主存储器的需要的紧急性确定的各种优先级的存储器请求信号的端口。 主存储器控制器将基于所接收的存储器请求信号的优先级和主系统的当前操作状态的紧迫性来确定是否对外围系统产生主存储器的控制。 结果是提高了计算机系统的整体效率。

公开(公告)号：US11614046B2

公开(公告)日：2023-03-28

申请号：US17736593

申请日：2022-05-04

申请人： Wen-Yi Wu

发明人： Wen-Yi Wu

IPC分类号： F02D41/22 ,  F02D17/04 ,  F02D41/10 ,  F02D41/16 ,  F02D41/04

摘要： The inhibition device includes a micro-controller configured with a triggering condition including a number of intervals and, for each interval, a corresponding duration and a corresponding threshold. Each interval is a range specifying how much the vehicle's acceleration pedal has changed its position in terms of percentages of a pedal stroke. Each duration specifies the fastest time duration allowable for the acceleration pedal to attain a corresponding interval of pedal position change. The micro-controller converts progress signals of the acceleration pedal to corresponding percentages, obtains a difference DEF between the successive percentages, records a time duration RES between successive progress signals, and calculates DEF/RES=X. When X is greater than or equal to a threshold of a corresponding interval, the micro-controller sends an idle signal to the vehicle's engine control unit or intercepts the progress signals to prevent them from reaching the engine control unit.

公开(公告)号：US11359571B2

公开(公告)日：2022-06-14

申请号：US17213194

申请日：2021-03-25

申请人： Wen-Yi Wu

发明人： Wen-Yi Wu

IPC分类号： F02D41/22 ,  F02D17/04 ,  F02D41/10 ,  F02D41/16 ,  F02D41/04

摘要： The inhibition device includes a micro-controller configured with a triggering condition including a number of intervals and, for each interval, a corresponding duration and a corresponding threshold. Each interval is a range specifying how much the vehicle's acceleration pedal has changed its position in terms of percentages of a pedal stroke. Each duration specifies the fastest time duration allowable for the acceleration pedal to attain a corresponding interval of pedal position change. The micro-controller converts progress signals of the acceleration pedal to corresponding percentages, obtains a difference DEF between the successive percentages, records a time duration RES between successive progress signals, and calculates DEF/RES=X. When X is greater than or equal to a threshold of a corresponding interval, the micro-controller sends an idle signal to the vehicle's engine control unit or intercepts the progress signals to prevent them from reaching the engine control unit.