公开(公告)号：US08407708B2

公开(公告)日：2013-03-26

申请号：US13211762

申请日：2011-08-17

Applicant: David Dice

Inventor： David Dice

IPC: G06F9/46 ,  G06F13/00

CPC classification number: G06F9/5033

Abstract: Techniques for controlling a thread on a computerized system having multiple processors involve accessing state information of a blocked thread, and maintaining the state information of the blocked thread at current values when the state information indicates that less than a predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such techniques further involve setting the state information of the blocked thread to identify affinity for a particular processor of the multiple processors when the state information indicates that at least the predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such operation enables the system to place a cold blocked thread which shares data with another thread on the same processor of that other thread so that, when the blocked thread awakens and runs, that thread is closer to the shared data.

Abstract translation: 用于控制具有多个处理器的计算机化系统上的线程的技术涉及访问被阻塞线程的状态信息，并且当状态信息指示自从该时间起经过了预定时间量时，将该线程的状态信息保持在当前值 阻塞的线程在计算机化系统上运行。 这种技术进一步涉及当状态信息指示自阻塞的线程在计算机化系统上运行以来经过了至少预定的时间量时，设置阻塞线程的状态信息以识别对多个处理器的特定处理器的亲和性。 这样的操作使得系统能够将与另一个线程共享数据的冷的阻塞线程放置在该另一个线程的同一处理器上，使得当被阻塞的线程唤醒并运行时，该线程更接近共享数据。

公开(公告)号：US08402464B2

公开(公告)日：2013-03-19

申请号：US12325870

申请日：2008-12-01

Applicant: David Dice ,  Mark S. Moir

Inventor： David Dice ,  Mark S. Moir

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/466

Abstract: Transactional Lock Elision (TLE) may allow threads in a multi-threaded system to concurrently execute critical sections as speculative transactions. Such speculative transactions may abort due to contention among threads. Systems and methods for managing contention among threads may increase overall performance by considering both local and global execution data in reducing, resolving, and/or mitigating such contention. Global data may include aggregated and/or derived data representing thread-local data of remote thread(s), including transactional abort history, abort causal history, resource consumption history, performance history, synchronization history, and/or transactional delay history. Local and/or global data may be used in determining the mode by which critical sections are executed, including TLE and mutual exclusion, and/or to inform concurrency throttling mechanisms. Local and/or global data may also be used in determining concurrency throttling parameters (e.g., delay intervals) used in delaying a thread when attempting to execute a transaction and/or when retrying a previously aborted transaction.

Abstract translation: 事务锁定Elision（TLE）可允许多线程系统中的线程同时执行关键部分作为投机事务。 这种投机交易可能由于线程之间的争用而中止。 用于管理线程争用的系统和方法可以通过在减少，解决和/或减轻这种争用时考虑本地和全局执行数据来增加总体性能。 全局数据可以包括表示远程线程的线程本地数据的聚合和/或导出数据，包括事务中止历史，中止因果历史，资源消耗历史，性能历史，同步历史和/或事务延迟历史。 本地和/或全局数据可用于确定执行关键段的模式，包括TLE和互斥，和/或通知并发调节机制。 本地和/或全局数据也可用于确定在尝试执行事务时和/或重试先前中止的事务时用于延迟线程的并发调节参数（例如，延迟间隔）。

公开(公告)号：US08332374B2

公开(公告)日：2012-12-11

申请号：US12101316

申请日：2008-04-11

Applicant: Yosef Lev ,  Nir N. Shavit ,  David Dice ,  Mark A. Moir

Inventor： Yosef Lev ,  Nir N. Shavit ,  David Dice ,  Mark A. Moir

IPC: G06F7/00 ,  G06F17/00 ,  G06F13/14

CPC classification number: G06F9/466 ,  G06F9/526

Abstract: Apparatus, methods, and program products are disclosed that provide a technology that implicitly isolates a portion of a transactional memory that is shared between multiple threads for exclusive use by an isolating thread without the possibility of other transactions modifying the isolated portion of the transactional memory. In some of the described embodiments read locations of a shared memory are covered by a first set of lock objects, and write locations are covered by a second set of lock objects, each lock object in each set having a reader mode and a writer mode. Some of these embodiments acquiring each lock object in the first set using the reader mode, and acquire each lock object in the second set using the writer mode. These embodiments store result data values at write locations in the shared memory subsequent to the acquiring said first and second set of lock objects.

Abstract translation: 公开了装置，方法和程序产品，其提供隐含地隔离在多个线程之间共享的事务存储器的一部分以供隔离线程独占使用的技术，而不会有其他事务修改事务存储器的隔离部分的可能性。 在一些描述的实施例中，共享存储器的读取位置由第一组锁定对象覆盖，并且写入位置由第二组锁定对象覆盖，每个组中的每个锁定对象具有读取器模式和写入器模式。 这些实施例中的一些实施例使用读取器模式来获取第一组中的每个锁定对象，并且使用写入器模式来获取第二组中的每个锁定对象。 这些实施例在获取所述第一和第二组锁定对象之后将结果数据值存储在共享存储器中的写入位置处。

公开(公告)号：US20110302585A1

公开(公告)日：2011-12-08

申请号：US13211762

申请日：2011-08-17

Applicant: David Dice

Inventor： David Dice

IPC: G06F9/46

CPC classification number: G06F9/5033

Abstract: Techniques for controlling a thread on a computerized system having multiple processors involve accessing state information of a blocked thread, and maintaining the state information of the blocked thread at current values when the state information indicates that less than a predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such techniques further involve setting the state information of the blocked thread to identify affinity for a particular processor of the multiple processors when the state information indicates that at least the predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such operation enables the system to place a cold blocked thread which shares data with another thread on the same processor of that other thread so that, when the blocked thread awakens and runs, that thread is closer to the shared data.

Abstract translation: 用于控制具有多个处理器的计算机化系统上的线程的技术涉及访问被阻塞线程的状态信息，并且当状态信息指示自从该时间起经过了预定的一段时间时，将被阻塞的线程的状态信息保持在当前值 阻塞的线程在计算机化系统上运行。 这种技术进一步涉及当状态信息指示自阻塞的线程在计算机化系统上运行以来经过了至少预定的时间量时，设置阻塞线程的状态信息以识别对多个处理器的特定处理器的亲和性。 这样的操作使得系统能够将与另一个线程共享数据的冷的阻塞线程放置在该另一个线程的同一处理器上，使得当被阻塞的线程唤醒并运行时，该线程更接近共享数据。

公开(公告)号：US20100138841A1

公开(公告)日：2010-06-03

申请号：US12325870

申请日：2008-12-01

Applicant: David Dice ,  Mark S. Moir

Inventor： David Dice ,  Mark S. Moir

IPC: G06F9/46

CPC classification number: G06F9/466

Abstract: Transactional Lock Elision (TLE) may allow threads in a multi-threaded system to concurrently execute critical sections as speculative transactions. Such speculative transactions may abort due to contention among threads. Systems and methods for managing contention among threads may increase overall performance by considering both local and global execution data in reducing, resolving, and/or mitigating such contention. Global data may include aggregated and/or derived data representing thread-local data of remote thread(s), including transactional abort history, abort causal history, resource consumption history, performance history, synchronization history, and/or transactional delay history. Local and/or global data may be used in determining the mode by which critical sections are executed, including TLE and mutual exclusion, and/or to inform concurrency throttling mechanisms. Local and/or global data may also be used in determining concurrency throttling parameters (e.g., delay intervals) used in delaying a thread when attempting to execute a transaction and/or when retrying a previously aborted transaction.

Abstract translation: 事务锁定Elision（TLE）可允许多线程系统中的线程同时执行关键部分作为投机事务。 这种投机交易可能由于线程之间的争用而中止。 用于管理线程争用的系统和方法可以通过在减少，解决和/或减轻这种争用时考虑本地和全局执行数据来增加总体性能。 全局数据可以包括表示远程线程的线程本地数据的聚合和/或导出的数据，包括事务中止历史，中止因果历史，资源消耗历史，性能历史，同步历史和/或事务延迟历史。 本地和/或全局数据可用于确定执行关键段的模式，包括TLE和互斥，和/或通知并发调节机制。 本地和/或全局数据也可用于确定在尝试执行事务时和/或重试先前中止的事务时用于延迟线程的并发调节参数（例如，延迟间隔）。

公开(公告)号：US07669040B2

公开(公告)日：2010-02-23

申请号：US11640018

申请日：2006-12-15

Applicant: David Dice

Inventor： David Dice

IPC: G06F12/16

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

Abstract: A system that executes a long transaction in a system with limited transactional hardware resources. During operation, the system executes the long transaction in a non transactional mode, which does not use transactional hardware resources. The system defers stores generated during the long transaction so that the stores are not committed to the architectural state of a processor until the transaction is successfully completed. If the long transaction successfully completes, the system commits the long transaction, which involves performing multiple hardware transactions to commit the deferred stores to the architectural state of the processor.

Abstract translation: 在具有有限的事务性硬件资源的系统中执行长事务的系统。 在操作过程中，系统执行非交易模式下，不使用事务的硬件资源的长事务。 该系统推迟长事务，使得存储不确认的处理器的体系结构状态，直到事务被成功地完成期间所产生的商店。 如果长事务成功完成，则系统提交长事务，其涉及执行多个硬件事务以将延迟存储提交到处理器的体系结构状态。

公开(公告)号：US07318128B1

公开(公告)日：2008-01-08

申请号：US10633258

申请日：2003-08-01

Applicant: David Dice

Inventor： David Dice

IPC: G06F12/06

CPC classification number: G06F9/5033 ,  G06F2209/485

Abstract: Mechanisms and techniques operate in a multiprocessing computer system having a plurality of processing devices and provide an affinity-based wakeup locality successor selection process that can identify processes to be executed by a kernel by detecting when a first process executing on a first processing device releases access to shared data. In response to the first process releasing access to the shared data, embodiments attempt to identify a second process that i) formerly executed on the first processing device and that ii) is awaiting access to the shared data. Embodiments provide, to a kernel responsible for selecting processes to execute amongst the plurality of processing devices, an identification of the second process as a process that is ready for execution in the multiprocessing computer system. Such embodiments can operate in an execution environment such as a Java Virtual Machine.

Abstract translation: 机构和技术在具有多个处理装置的多处理计算机系统中操作，并且提供基于亲和性的唤醒位置性后继选择过程，其可以通过检测在第一处理设备上执行的第一进程何时释放访问来识别由内核执行的进程 共享数据。 响应于释放对共享数据的访问的第一处理，实施例尝试识别i）以前在第一处理设备上执行并且ii）等待访问共享数据的第二进程。 实施例向负责选择在多个处理装置之间执行的进程的内核提供作为准备在多处理计算机系统中执行的处理的第二进程的标识。 这样的实施例可以在诸如Java虚拟机的执行环境中操作。

公开(公告)号：US20070198519A1

公开(公告)日：2007-08-23

申请号：US11475814

申请日：2006-06-27

Applicant: David Dice ,  Ori Shalev ,  Nir Shavit

Inventor： David Dice ,  Ori Shalev ,  Nir Shavit

IPC: G06F17/30

CPC classification number: G06F12/0806 ,  G06F9/466 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0893

Abstract: The present disclosure describes a unique way for each of multiple processes to operate in parallel using (e.g., reading, modifying, and writing to) the same shared data without causing corruption to the shared data. For example, each of multiple processes utilizes current and past data values associated with a global counter or clock for purposes of determining whether any shared variables used to produce a respective transaction outcome were modified (by another process) when executing a respective transaction. If a respective process detects that shared data used by respective process was modified during a transaction, the process can abort and retry the transaction rather than cause data corruption by storing locally maintained results associated with the transaction to a globally shared data space.

Abstract translation: 本公开描述了使用（例如，读取，修改和写入）相同的共享数据而不会对共享数据造成损坏的多个进程中的每一个进行并行操作的独特方式。 例如，当执行相应的交易时，多个过程中的每个利用与全局计数器或时钟相关联的当前和过去的数据值来确定用于产生相应的交易结果的任何共享变量（通过另一个进程）被修改。 如果相应的进程检测到在处理期间修改了相应进程使用的共享数据，则该进程可以中止并重试事务，而不是通过将与事务相关联的本地维护的结果存储到全局共享的数据空间来导致数据损坏。

公开(公告)号：US07178062B1

公开(公告)日：2007-02-13

申请号：US10386593

申请日：2003-03-12

Applicant: David Dice

Inventor： David Dice

IPC: G06F11/00

CPC classification number: G06F9/524 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/30087

Abstract: Mechanisms and techniques operate in a scalable or non-scalable processing architecture computerized device to execute critical code while overcoming interference from interruptions. A critical signal handler is registered and a non-operating system thread sets a value of a critical code register to indicate a critical execution condition. The non-operating system thread then executes a critical code section until an interruption occurs. In response to the interruption to the critical code section, an operating system thread detects if the critical code register is equivalent to a critical execution condition and if so, sets the value of the critical code register to indicate a critical execution failure. Upon returning to execution of the critical code section, the critical code section attempts to execute a contingent instruction in the critical code section that is contingent upon the value of the critical code register. The attempted execution of the contingent instruction triggers a critical trap signal when the critical code register is set to a value that indicates the critical execution failure. The critical execution signal handler processes the critical trap signal to avoid any interference that may have been caused by the interruption.

Abstract translation: 机制和技术在可扩展或不可扩展的处理架构计算机化设备中运行，以执行关键代码，同时克服来自中断的干扰。 注册关键信号处理程序，非操作系统线程设置关键代码寄存器的值以指示关键执行条件。 然后，非操作系统线程执行关键代码段，直到发生中断。 响应于关键代码段的中断，操作系统线程检测关键代码寄存器是否等同于关键执行条件，如果是，则将关键代码寄存器的值设置为指示关键执行失败。 当关键代码部分返回执行时，关键代码部分尝试在关键代码部分执行依赖于关键代码寄存器的值的或有指令。 当临界代码寄存器设置为指示关键执行失败的值时，尝试执行或有指令会触发关键陷阱信号。 关键执行信号处理器处理关键陷阱信号，以避免可能由中断引起的任何干扰。

公开(公告)号：US06799236B1

公开(公告)日：2004-09-28

申请号：US10044214

申请日：2001-11-20

Applicant: David Dice ,  Alexander T. Garthwaite

Inventor： David Dice ,  Alexander T. Garthwaite

IPC: G06F1214

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087

Abstract: Mechanisms and techniques operate in a computerized device to execute critical code without interference from interruptions. Critical code is registered for invocation of a critical execution manager in the event of an interruption to the critical code. The critical code is then executed until an interruption to the critical code occurs. After handling the interruption, a critical execution manager is invoked and the critical execution manager detects if an interference signal indicates a reset value. If the interference signal indicates the reset value, the critical execution manager performs a reset operation on the critical code to reset a current state of the critical code to allow execution of the critical code while avoiding interference from handling the interruption and returns to execution of the critical code using the current state of the critical code.

Abstract translation: 机制和技术在计算机化设备中运行，以执行关键代码，而不受中断的干扰。 在关键代码中断的情况下，注册关键代码用于调用关键执行管理器。 然后执行关键代码，直到出现关键代码的中断。 处理中断后，调用关键执行管理器，关键执行管理器检测干扰信号是否指示复位值。 如果干扰信号指示复位值，则关键执行管理器对关键代码执行复位操作，以重置关键代码的当前状态，以允许执行关键代码，同时避免干扰来处理中断并返回执行 关键代码使用关键代码的当前状态。