公开(公告)号：US09159633B2

公开(公告)日：2015-10-13

申请号：US14026172

申请日：2013-09-13

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括形成具有第一和第二栅极区的测试宏的有源区，并在有源区中形成第一和第二源极/漏极区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点。 该方法还包括通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路来确定在形成有源区域期间是否发生覆盖偏移。

公开(公告)号：US08816428B1

公开(公告)日：2014-08-26

申请号：US13905850

申请日：2013-05-30

Applicant: International Business Machines Corporation ,  Global Foundries Inc.

Inventor： Robert J. Miller ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L21/762 ,  H01L29/66795

Abstract: Methods and systems for forming multigate devices and systems are disclosed. In accordance with one such method, a fin is formed on a semiconductor substrate including a carbon-doped semiconductor layer. Further, a first portion of semiconductor material that is beneath the fin is removed to form a void beneath the fin by etching the material such that the fin is supported by at least one supporting pillar of the semiconducting material and such that the carbon-doped semiconductor layer prevents the etching from removing at least a portion of the fin. A dielectric material is deposited in the void to isolate the fin from a second portion of semiconductor material that is below the void. In addition, source and drain regions are formed in the fin and a gate structure is formed over the fin to fabricate the multigate device such that the dielectric material reduces current leakage beneath the device.

Abstract translation: 公开了用于形成多设备和系统的方法和系统。 根据一种这样的方法，在包括碳掺杂半导体层的半导体衬底上形成翅片。 此外，在翅片下面的半导体材料的第一部分被去除以通过蚀刻材料形成鳍下方的空隙，使得翅片由半导体材料的至少一个支撑柱支撑，并且使得掺杂碳的半导体 层防止蚀刻去除鳍的至少一部分。 在空隙中沉积介电材料以将散热片与空隙下方的半导体材料的第二部分隔离。 此外，源极和漏极区域形成在翅片中，并且在鳍上形成栅极结构以制造多栅极器件，使得介电材料减少器件下方的电流泄漏。