中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

72 records (took 0.02 seconds)

    Reducing Resistivity in Interconnect Structures of Integrated Circuits
    52.
    发明申请
    Reducing Resistivity in Interconnect Structures of Integrated Circuits 有权
    集成电路互连结构中的降低电阻率

    公开(公告)号：US20110171826A1

    公开(公告)日：2011-07-14

    申请号：US13036599

    申请日：2011-02-28

    Applicant: Cheng-Lin Huang

    Inventor： Cheng-Lin Huang

    IPC: H01L21/768

    CPC classification number: H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856

    Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

    Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。

    Cleaning processes in the formation of integrated circuit interconnect structures
    54.
    发明申请
    Cleaning processes in the formation of integrated circuit interconnect structures 有权
    形成集成电路互连结构的清洁过程

    公开(公告)号：US20080124919A1

    公开(公告)日：2008-05-29

    申请号：US11593286

    申请日：2006-11-06

    Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC: H01L21/4763

    CPC classification number: H01L21/02063 ,  H01L21/76807 ,  H01L21/76814

    Abstract: A method for fabricating an integrated circuit includes providing a substrate, forming a low-k dielectric layer over the substrate, etching the low-k dielectric layer to form an opening in the low-k dielectric layer wherein an underlying metal is exposed through the opening, performing a remote plasma treatment to the substrate wherein a plasma used for the remote plasma treatment is generated from a plasma generator separated from a chamber in which the substrate is located, forming a diffusion barrier layer in the opening, and filling the opening with a conductive material. The method preferably includes an in-situ plasma treatment in a same chamber as the step of etching the low-k dielectric layer.

    Abstract translation: 一种用于制造集成电路的方法包括提供衬底，在衬底上形成低k电介质层，蚀刻低k电介质层以在低k电介质层中形成开口，其中下面的金属通过开口暴露 对基板执行远程等离子体处理，其中用于远程等离子体处理的等离子体从与其中所述基板所在的室分离的等离子体发生器产生，在该开口中形成扩散阻挡层，并且在该开口中填充该开口 导电材料。 该方法优选包括在与蚀刻低k电介质层的步骤相同的室中的原位等离子体处理。

    Barrier layer and fabrication method thereof
    55.
    发明授权
    Barrier layer and fabrication method thereof 有权
    阻挡层及其制造方法

    公开(公告)号：US07179759B2

    公开(公告)日：2007-02-20

    申请号：US10955519

    申请日：2004-09-30

    Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC: H01L21/31 ,  H01L21/469

    CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76826 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A barrier layer and a fabrication thereof are disclosed. The barrier layer comprises at least one barrier material selected from the group consisting of Ta, W, Ti, Ru, Zr, Hf, V, Nb, Cr and Mo and at least one component of oxygen, nitrogen or carbon. A ratio of the component to the barrier material is not less than about 0.45. The fabrication method of the barrier layer applies a working pressure for forming the barrier layer from about 0.5 mTorr to about 200 mTorr substantially without forming crystalline material therein.

    Abstract translation: 公开了阻挡层及其制造。 阻挡层包含选自Ta，W，Ti，Ru，Zr，Hf，V，Nb，Cr和Mo中的至少一种阻挡材料和氧，氮或碳的至少一种成分。 组分与阻隔材料的比例不小于约0.45。 阻挡层的制造方法施加用于形成阻挡层的工作压力，大约0.5mTorr至大约200mTorr，基本上不形成结晶材料。

    Reducing resistivity in interconnect structures of integrated circuits
    56.
    发明授权
    Reducing resistivity in interconnect structures of integrated circuits 有权
    降低集成电路互连结构中的电阻率

    公开(公告)号：US08426307B2

    公开(公告)日：2013-04-23

    申请号：US13036599

    申请日：2011-02-28

    Applicant: Cheng-Lin Huang

    Inventor： Cheng-Lin Huang

    IPC: H01L21/4763

    CPC classification number: H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856

    Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

    Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。

    Methods for Via Structure with Improved Reliability
    57.
    发明申请
    Methods for Via Structure with Improved Reliability 有权
    通过结构改进可靠性的方法

    公开(公告)号：US20120322261A1

    公开(公告)日：2012-12-20

    申请号：US13595835

    申请日：2012-08-27

    Applicant: Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

    Inventor： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

    IPC: H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.

    Abstract translation: 提供了形成通孔结构的方法。 该方法包括在半导体衬底上沉积第一层导电线，在第一层导电线上形成电介质层，在电介质层中形成通孔，并在通路孔中露出第一层导电线，形成 在第一层导电线中的凹陷部分，并且填充通孔开口以形成延伸通过介电层到第一层导电线的通孔。 通孔具有基本上锥形的轮廓并且基本上延伸到第一层导电线中的凹部中。

    Reducing resistivity in interconnect structures of integrated circuits
    59.
    发明授权
    Reducing resistivity in interconnect structures of integrated circuits 有权
    降低集成电路互连结构中的电阻率

    公开(公告)号：US07919862B2

    公开(公告)日：2011-04-05

    申请号：US11429879

    申请日：2006-05-08

    Applicant: Cheng-Lin Huang

    Inventor： Cheng-Lin Huang

    IPC: H01L23/52

    CPC classification number: H01L21/76834 ,  H01L21/76831

    Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

    Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。

Patent Agency Ranking