公开(公告)号：US20110006429A1

公开(公告)日：2011-01-13

申请号：US12832790

申请日：2010-07-08

Applicant: Nai-Wei LIU ,  Zhen-Cheng WU ,  Cheng-Lin HUANG ,  Po-Hsiang HUANG ,  Yung-Chih WANG ,  Shu-Hui SU ,  Dian-Hau CHEN ,  Yuh-Jier MII

Inventor： Nai-Wei LIU ,  Zhen-Cheng WU ,  Cheng-Lin HUANG ,  Po-Hsiang HUANG ,  Yung-Chih WANG ,  Shu-Hui SU ,  Dian-Hau CHEN ,  Yuh-Jier MII

IPC: H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/76831 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract translation: 铜互连包括形成在电介质层中的铜层，具有第一部分和第二部分。 在铜层的第一部分和电介质层之间形成第一阻挡层。 在铜层的第二部分和电介质层之间的边界处形成第二阻挡层。 第一阻挡层是电介质层，第二阻挡层是金属氧化物层。

公开(公告)号：US20130207276A1

公开(公告)日：2013-08-15

申请号：US13397488

申请日：2012-02-15

Applicant: Uway Tseng ,  Shu-Hui Su

Inventor： Uway Tseng ,  Shu-Hui Su

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括形成在衬底上的第一金属层部件。 半导体器件包括形成在第一金属层部件上的通孔。 通孔具有凹陷形状。 半导体器件包括在通孔上形成的第二金属层元件。 半导体器件包括形成在衬底上的第一介电层组件。 第一介电层组件位于第一金属层组件附近并部分地位于第一金属层组件上。 第一介电层组分含氟。 半导体器件包括形成在第一介电层部件上的第二介电层部件。 第一电介质层组分和第二介电层组分各自位于与通孔相邻的位置。 第二介电层组分不含氟。

公开(公告)号：US08456009B2

公开(公告)日：2013-06-04

申请号：US12707969

申请日：2010-02-18

Applicant: Shu-Hui Su ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mii

Inventor： Shu-Hui Su ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mii

IPC: H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/02203 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract translation: 半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。 第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料限定的气隙区，并邻接 该组金属结构的至少一部分。 第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。 导电焊盘和通孔插头不与气隙区域重叠。

公开(公告)号：US20110198757A1

公开(公告)日：2011-08-18

申请号：US12707969

申请日：2010-02-18

Applicant: Shu-Hui SU ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mll

Inventor： Shu-Hui SU ,  Cheng-Lin Huang ,  Jiing-Feng Yang ,  Zhen-Cheng Wu ,  Ren-Guei Wu ,  Dian-Hau Chen ,  Yuh-Jier Mll

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  G03F1/00

CPC classification number: H01L23/5226 ,  H01L21/02203 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract translation: 半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。 第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料界定的气隙区， 该组金属结构的至少一部分。 第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。 导电焊盘和通孔插头不与气隙区域重叠。

公开(公告)号：US08716871B2

公开(公告)日：2014-05-06

申请号：US13397488

申请日：2012-02-15

Applicant: Uway Tseng ,  Shu-Hui Su

Inventor： Uway Tseng ,  Shu-Hui Su

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

Abstract translation: 一种半导体器件，包括在衬底上形成的第一金属层组件。 半导体器件包括形成在第一金属层部件上的通孔。 通孔具有凹陷形状。 半导体器件包括在通孔上形成的第二金属层元件。 半导体器件包括形成在衬底上的第一介电层组件。 第一介电层组件位于第一金属层组件附近并部分地位于第一金属层组件上。 第一介电层组分含氟。 半导体器件包括形成在第一介电层部件上的第二介电层部件。 第一电介质层组分和第二介电层组分各自位于与通孔相邻的位置。 第二介电层组分不含氟。

公开(公告)号：US08653664B2

公开(公告)日：2014-02-18

申请号：US12832790

申请日：2010-07-08

Applicant: Nai-Wei Liu ,  Zhen-Cheng Wu ,  Cheng-Lin Huang ,  Po-Hsiang Huang ,  Yung-Chih Wang ,  Shu-Hui Su ,  Dian-Hau Chen ,  Yuh-Jier Mii

Inventor： Nai-Wei Liu ,  Zhen-Cheng Wu ,  Cheng-Lin Huang ,  Po-Hsiang Huang ,  Yung-Chih Wang ,  Shu-Hui Su ,  Dian-Hau Chen ,  Yuh-Jier Mii

IPC: H01L23/522 ,  H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/76831 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract translation: 铜互连包括形成在电介质层中的铜层，具有第一部分和第二部分。 在铜层的第一部分和电介质层之间形成第一阻挡层。 在铜层的第二部分和电介质层之间的边界处形成第二阻挡层。 第一阻挡层是电介质层，第二阻挡层是金属氧化物层。